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publication number S29PL-J_00 revision a amendment 9 issue date september 22, 2006 S29PL-J S29PL-J cover sheet 128/128/64/32 megabit (8/8/4/2 m x 16-bit) cmos 3.0 volt-only, simultaneous-read/write flash memory with enhanced versatileio? control data sheet (advance information) notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product describ ed herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
ii S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office.
this document contains information on one or more products under development at spansion inc. the information is intended to he lp you evaluate this product. do not design in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed pr oduct without notice. publication number S29PL-J_00 revision a amendment 9 issue date september 22, 2006 distinctive characteristics architectural advantages ? 128/128/64/32 mbit page mode devices ? page size of 8 words: fast page read access from random locations within the page ? single power supply operation ? full voltage range: 2.7 to 3.6 volt read, erase, and program operations for battery-powered applications ? dual chip enable inputs (only in pl129j) ? two ce# inputs control selection of each half of the memory space ? simultaneous read/write operation ? data can be continuously read from one bank while executing erase/ program functions in another bank ? zero latency switching from write to read operations ? flexbank architecture (pl127j/pl064j/pl032j) ? 4 separate banks, with up to two simultaneous operations per device ? bank a: pl127j -16 mbit (4 kw x 8 and 32 kw x 31) pl064j - 8 mbit (4 kw x 8 and 32 kw x 15) pl032j - 4 mbit (4 kw x 8 and 32 kw x 7) ? bank b: pl127j - 48 mbit (32 kw x 96) pl064j - 24 mbit (32 kw x 48) pl032j - 12 mbit (32 kw x 24) ? bank c: pl127j - 48 mbit (32 kw x 96) pl064j - 24 mbit (32 kw x 48) pl032j - 12 mbit (32 kw x 24) ? bank d: pl127j -16 mbit (4 kw x 8 and 32 kw x 31) pl064j - 8 mbit (4 kw x 8 and 32 kw x 15) pl032j - 4 mbit (4 kw x 8 and 32 kw x 7) ? flexbank architecture (pl129j) ? 4 separate banks, with up to two simultaneous operations per device ? ce#1 controlled banks: bank 1a: pl129j - 16mbit (4kw x 8 and 32kw x 31) bank 1b: pl129j - 48mbit (32kw x 96) ? ce#2 controlled banks: bank 2a: pl129j - 48 mbit (32kw x 96) bank 2b: pl129j - 16mbit (4kw x 8 and 32kw x 31) ? enhanced versatilei/o (v io ) control ? output voltage generated and input voltages tolerated on all control inputs and i/os is determined by the voltage on the v io pin ?v io options at 1.8 v and 3 v i/o for pl127j and pl129j devices ?3v v io for pl064j and pl032j devices ? secured silicon sector region ? up to 128 words accessible through a command sequence ? up to 64 factory-locked words ? up to 64 customer-lockable words ? both top and bottom boot blocks in one device ? manufactured on 110 nm process technology ? data retention: 20 years typical ? cycling endurance: 1 million cycles per sector typical performance characteristics ? high performance ? page access times as fast as 20 ns ? random access times as fast as 55 ns ? power consumption (typical values at 10 mhz) ? 45 ma active read current ? 17 ma program/erase current ? 0.2 a typical standby mode current software features ? software command-set compatible with jedec 42.4 standard ? backward compatible with am29f, am29lv, am29dl, and am29pdl families and mbm29qm/rm, mbm29lv, mbm29dl, mbm29pdl families ? cfi (common flash interface) compliant ? provides device-specific information to the system, allowing host software to easily reconfigure for different flash devices ? erase suspend / erase resume ? suspends an erase operation to allow read or program operations in other sectors of same bank ? program suspend / program resume ? suspends a program operation to allow read operation from sectors other than the one being programmed ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences hardware features ? ready/busy# pin (ry/by#) ? provides a hardware method of detecting program or erase cycle completion ? hardware reset pin (reset#) ? hardware method to reset the device to reading array data ? wp#/ acc (write protect/acceleration) input ?at v il , hardware level protection for the first and last two 4k word sectors. ?at v ih , allows removal of sector protection ?at v hh , provides accelerated programming in a factory setting ? persistent sector protection ? a command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector ? sectors can be locked and unlocked in-system at v cc level ? password sector protection ? a sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password ? package options ? standard discrete pinouts 11 x 8 mm, 80-ball fine-pitch bga (pl127j) (vbg080) 8.15 x 6.15 mm, 48-ball fine pitch bga (pl064j/pl032j) (vbk048) ? mcp-compatible pinout 8 x 11.6 mm, 64-ball fine-pitch bga (pl127j) 7 x 9 mm, 56-ball fine-pitch bga (pl064j and pl032j) compatible with mcp pinout, allowi ng easy integration of ram into existing designs ? 20 x 14 mm, 56-pin tsop (pl127j) (ts056) S29PL-J 128/128/64/32 megabit (8/8/4/2 m x 16-bit) cmos 3.0 volt-only, simultaneous-read/write flash memory with enhanced versatileio? control data sheet (advance information)
2 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) general description the pl127j/pl129j/pl064j/pl032j is a 128/128/64/32 mbit, 3.0 volt-only page mode and simultaneous read/write flash memory device organized as 8/8/4/ 2 mwords. the devices are offered in the following packages: ? 11 mm x 8 mm, 80-ball fine-pitch bga standalone (pl127j) ? 8 mm x 11.6 mm, 64-ball fine-pitch bga multi-chip compatible (pl127j) ? 8.15 mm x 6.15 mm, 48-ball fine-pitc h bga standalone (pl064j/pl032j) ? 7 mm x 9 mm, 56-ball fine-pitch bga multi-chip compatible (pl064j and pl032j) ? 20 mm x 14 mm, 56-pin tsop (pl127j) the word-wide data (x16) app ears on dq15-dq0. this device can be pr ogrammed in-system or in standard eprom programmers. a 12.0 v v pp is not required for write or erase operations. the device offers fast page access times of 20 to 30 ns, with corresponding random access times of 55 to 70 ns, respectively, allowing high speed microprocessors to operate without wait states. to eliminate bus contention the device has separate chip enable (ce# ), write enable (we#) and output enable (oe#) controls. note: device pl129j has 2 chip enable inputs (ce1#, ce2#).
september 22, 2006 S29PL-J_00_a9 S29PL-J 3 data sheet (advance information) table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1. simultaneous read/write op eration with zero latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 page mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 standard flash memory features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3. product selector guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5. simultaneous read/write block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. simultaneous read/write block diagram (pl129j) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7. connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1 special package handling instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 80-ball fine-pitch bga?pl127j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.3 64-ball fine-pitch bga?mcp compatible?pl127j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4 48-ball fine-pitch bga, pl064j and pl032j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.5 56-pin tsop 20 x 14 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.6 56-ball fine-pitch ball grid array, pl064j and pl032j . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9. logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10. device bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10.1 requirements for reading array data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10.2 simultaneous read/write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.3 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10.4 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10.5 automatic sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10.6 reset#: hardware reset pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10.7 output disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10.8 autoselect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.9 selecting a sector protection mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11. sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.1 persistent sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.2 password sector protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.3 wp# hardware protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.4 selecting a sector protection mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12. persistent sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.1 persistent protection bit (ppb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.2 persistent protection bit lock (ppb lock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.3 dynamic protection bit (dyb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.4 persistent sector protection mode locking bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13. password protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.1 password and password mode locking bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.2 64-bit password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.3 write protect (wp#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13.4 high voltage sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13.5 temporary sector unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.6 secured silicon sector flash memory region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.7 hardware data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 14. common flash memory interface (cfi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 15. command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 15.1 reading array data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 15.2 reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 15.3 autoselect command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 15.4 enter/exit secured silicon sector command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 15.5 word program command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 15.6 chip erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 15.7 sector erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.8 erase suspend/erase resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 15.9 program suspend/program resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 15.10 command definitions tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 16. write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 16.1 dq7: data# polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 16.2 ry/by#: ready/busy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 16.3 dq6: toggle bit i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 16.4 dq2: toggle bit ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 16.5 reading toggle bits dq6/dq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 16.6 dq5: exceeded timing limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 16.7 dq3: sector erase timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 17. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 18. operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 19. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 20. ac characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 20.1 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 20.2 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 20.3 v cc ramp rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 20.4 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 20.5 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 20.6 erase/program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 20.7 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 21. protect/unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 21.1 controlled erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 22. bga pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 23. physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 23.1 vbg080?80-ball fine-pitch ball grid array 8 x 11 mm package (pl127j) . . . . . . . . . . . . . 86 23.2 vbh064?64-ball fine-pitch ball grid array 8 x 11.6 mm package (pl127j). . . . . . . . . . . . 87 23.3 vbk048?48-ball fine-pitch ball grid array 8.15 x 6.15 mm package (pl032j and pl064j) 88 23.4 vbu056?56-ball fine-pitch bga 7 x 9mm package (pl064j and pl032j) . . . . . . . . . . . . 89 23.5 ts056?20 x 14 mm, 56-pin tsop (pl127j) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 24. revision summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 24.1 revision a0 (january 29, 2004). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 24.2 revision a1 (february 12, 2004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 24.3 revision a2 (february 17, 2004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 24.4 revision a3 (february 25, 2004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 24.5 revision a4 (february 27, 2004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 24.6 revision a5 (march 15, 2004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 24.7 revision a6 (august 30, 2004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 24.8 revision a7 (march 2, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 24.9 revision a8 (july 29, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 24.10 revision a9 (september 22, 2006) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
september 22, 2006 S29PL-J_00_a9 S29PL-J 5 data sheet (advance information) list of tables table 10.1 pl127j device bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 10.2 pl129j device bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 10.3 page select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 10.4 bank select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 10.5 pl127j sector architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 10.6 pl064j sector architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 10.7 pl032j sector architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 10.8 s29pl129j sector architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 10.9 secured silicon sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 10.10 autoselect codes (high voltage method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 10.11 autoselect codes for pl129j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 10.12 pl127j boot sector/sector block addresses fo r protection/unprotection . . . . . . . . . . . . . . .41 table 10.13 pl129j boot sector/sector block addresses fo r protection/unprotection . . . . . . . . . . . . . . .42 table 10.14 pl064j boot sector/sector block addresses fo r protection/unprotection . . . . . . . . . . . . . . .43 table 10.15 sector protection schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 14.1 cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 14.2 system interface string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 14.3 device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 14.4 primary vendor-specific extended query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 15.1 memory array command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 table 15.2 sector protection command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 table 16.1 write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 table 19.1 cmos compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 table 20.1 test specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 table 20.2 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 table 20.3 read-only operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 table 20.4 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 table 20.5 erase and program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 table 21.1 temporary sector unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 table 21.2 alternate ce# controlled erase and program operati ons . . . . . . . . . . . . . . . . . . . . . . . . . . .83 table 21.3 ce1#/ce2# timing (s29pl129j only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 table 21.4 erase and programming performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) list of figures figure 7.1 80-ball fine-pitch bg a, top view, balls facing down?pl127j . . . . . . . . . . . . . . . . . . . . . 14 figure 7.2 64-ball fine-pitch bga, mcp compatible, top view, balls facing down?pl127j . . . . . . 15 figure 7.3 48-ball fine-pitch bga, top view, balls facing down?pl064j?pl032j: c4(a21)=nc . . . 16 figure 7.4 56-pin tsop 20 x 14 mm configuration?pl127j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7.5 56-ball fine-pitch bga, top view, balls facing down,?pl064j and pl032j,. . . . . . . . . . . 18 figure 13.1 in-system sector protection/sector unprotection al gorithms . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 13.2 temporary sector unprotect operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 13.3 secured silicon sector protect verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 15.1 program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 15.2 erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 16.1 data# polling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 16.2 toggle bit algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 17.1 maximum overshoot waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 20.1 test setups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 20.2 input waveforms and measurement levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 20.3 read operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 20.4 page read operation timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 20.5 reset timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 20.6 program operation timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 20.7 accelerated program timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 20.8 chip/sector erase operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 20.9 back-to-back read/write cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 20.10 data# polling timings (during embedded algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 20.11 toggle bit timings (during embedded algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 20.12 dq2 vs. dq6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 21.1 temporary sector unprotect timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 21.2 sector/sector block protect and unprotect timing diagram . . . . . . . . . . . . . . . . . . . . . . . . .82 figure 21.3 alternate ce# controlled write (erase/program) o peration timings . . . . . . . . . . . . . . . . . . .83 figure 21.4 timing diagram for alternating between ce1# and ce2# control . . . . . . . . . . . . . . . . . . . . 84
september 22, 2006 S29PL-J_00_a9 S29PL-J 7 data sheet (advance information) 1. simultaneous read/write op eration with zero latency the simultaneous read/write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be considered to be four separ ate memory arrays as far as certain operations are concerned. the device can improve overall system pe rformance by allowing a ho st system to program or erase in one bank, then immediately and simultaneousl y read from another bank with zero latency (with two simultaneous operations operating at any one time). this releases the system from waiting for the completion of a program or erase operation, gr eatly improving system performance. the device can be organized in both top and bottom sector configurations. the banks are organized as follows: 1.1 page mode features the page size is 8 words. after initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page. bank pl127j sectors pl064j sectors pl032j sectors a 16 mbit (4 kw x 8 and 32 kw x 31) 8 mbit (4 kw x 8 and 32 kw x 15) 4 mbit (4 kw x 8 and 32 kw x 7) b 48 mbit (32 kw x 96) 24 mbit (32 kw x 48) 12 mbit (32 kw x 24) c 48 mbit (32 kw x 96) 24 mbit (32 kw x 48) 12 mbit (32 kw x 24) d 16 mbit (4 kw x 8 and 32 kw x 31) 8 mbit (4 kw x 8 and 32 kw x 15) 4 mbit (4 kw x 8 and 32 kw x 7) bank pl129j sectors ce# control 1a 16 mbit (4 kw x 8 and 32 kw x 31) ce1# 1b 48 mbit (32 kw x 96) ce1# 2a 48 mbit (32 kw x 96) ce2# 2b 16 mbit (4 kw x 8 and 32 kw x 31) ce2#
8 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 1.2 standard flash memory features the device requires a single 3.0 volt power supply (2.7 v to 3.6 v) for both read and write functions. internally generated and regulated voltages ar e provided for the program and erase operations. the device is entirely command set compatible with the jedec 42.4 single-power -supply flash standard . commands are written to the command register usin g standard microprocessor write timing. register contents serve as inputs to an intern al state-machine that co ntrols the erase and prog ramming circuitry. write cycles also internally latch addresses and data n eeded for the programming and erase operations. reading data out of the device is similar to re ading from other flash or eprom devices. device programming occurs by executing the program command sequence. the unlock bypass mode facilitates faster programming times by requiring only two write cycles to pr ogram data instead of four. device erasure occurs by executing the erase command sequence. the host system can detect wh ether a program or erase operation is complete by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a program or erase cycle has been completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sector s to be erased and reprogra mmed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write operations during power transitions. the hardware sector protection feature disables both pr ogram and erase operations in any combination of sectors of memory. this c an be achieved in-system or via programming equipment. the erase suspen d/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to , any sector that is not selected fo r erasure. true background erase can thus be achieved. if a read is needed from the secu red silicon sector area (one time program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. the program suspend/program resume feature enables the user to hold the program operation to read data from any sector that is not se lected for programming. if a read is nee ded from the secured silicon sector area, persistent protection area, dy namic protection area, or the cfi area, after a program suspend, then the user must use the proper command s equence to enter and exit this region. the device offers two power-saving features. when add resses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode. power consumption is greatly reduced in both these modes. the device electrically erases all bits within a sector simultaneously via fowler-nordheim tunneling. the data is programmed using hot electron injection.
september 22, 2006 S29PL-J_00_a9 S29PL-J 9 data sheet (advance information) 2. ordering information the order number (valid combination) is form ed by a valid combinations of the following: valid combinations to be supported for this device S29PL-J 55 ba w 00 0 packing type 0=tray 1 = tube 2 = 7-inch tape and reel 3 = 13-inch tape and reel model number (additional ordering options) 00 = 3.0v v io , 80-ball 11 x 8 mm fbga (vbg080) 01 = 1.8v v io , 80-ball 11 x 8 mm fbga (vbg080) 02 = 3.0v v io , 64-ball 8 x 11.6 mm fbga (vbh064) 12 = 3.0v v io , 48-ball 8 x 6 mm fbga (vbk048) 13 = 3.0v v io , 56-ball 20 x 14 mm tsop (ts056) 15 = 3.0v v io , 56-ball 7 x 9 mm fbga (vbu056) temperature range w = wireless (?25c to +85c) i = industrial (?40c to +85c) package type ba = fine-pitch grid array (fbga) lead (pb)- free compliant bf = fine-pitch grid array (fbga) lead (pb)-free ta = thin small outline package (tsop) standard pinout lead (pb)-free compliant tf = thin small outline package (tsop) standard pinout lead (pb)-free clock speed 55 = 55 ns (contact factory for availability) 60 = 60 ns 65 = 65 ns 70 = 70 ns device number/description 128 megabit (8 m x 16-bit), 64 megabit (4 m x 16-bit), 32 megabit (2 m x 16-bit) cmos flash memory, simultaneous-read/write, page-mode flash memory, 3.0 volt-only read, program, and erase 128 mb products based on 110 nm floating gate technology device number/ description speed (ns) package type temperature range additional ordering options ce# configuration s29pl127j 55, 60, 65, 70 ba, bf, ta, tf w, i 00, 01, 13 single ce# 64 mb products based on 110 nm floating gate technology device number/ description speed (ns) package type temperature range additional ordering options s29pl064j 55, 60, 70 ba, bf w, i 12, 15 32 mb products based on 110 nm floating gate technology device number/ description speed (ns) package type temperature range additional ordering options s29pl032j 55, 60, 70 ba, bf w, i 12, 15
10 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) notes 1. please contact the factor y for pl129j availability. 2. please contact the factory for availability. 3. product selector guide note contact factory for availability valid combinations for bga packages order number (note 1) speed (ns) v io range pl129j, pl127j,pl064j, pl032j 55, 60, 65, 70 2.7?3.6 pl129j, pl127j 65, 70 1.65?1.95 valid combinations for tsop packages order number speed (ns) v io range s29pl127j 55, 60, 70 2.7?3.6 part number s29pl032j/s29pl064j/s29pl0127j/s29pl129j speed option v cc ,v io = 2.7 v ? 3.6 v 55 (see note) 60 65 ? ? 70 v cc = 2.7 v ? 3.6 v, v cc = 1.65 v ? 1.95 v (pl127j and pl129j only) ???6570? max access time, ns (t acc ) 55 (see note) 60 25 65 70 70 max ce# access, ns (t ce ) max page access, ns (t pac c ) 2 (see note) 25 25 30 30 max oe# access, ns (t oe )
september 22, 2006 S29PL-J_00_a9 S29PL-J 11 data sheet (advance information) 4. block diagram notes 1. ry/by# is an open drain output. 2. amax = a22 (pl127j), a21 (pl129j and pl064j), a20 (pl032j) 3. for pl129j there are two ce# (ce1# and ce2#) v cc v ss state control command register pgm voltage generator v cc detector timer erase voltage generator input/output buffers sector switches chip enable output enable logic y-gating cell matrix address latch y-decoder x-decoder data latch reset# ry/by# amax?a3 a2?a0 ce# we# dq15?dq0 v io oe#
12 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 5. simultaneous read/write block diagram note amax = a22 (pl127j), a21 (pl064j), a20 (pl032j) v cc v ss bank a address bank b address amax?a0 reset# we# ce# dq0?dq15 state control & command register ry/by# bank a x-decoder oe# dq15?dq0 status control amax?a0 amax?a0 a22?a0 a22?a0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 mux mux mux bank b x-decoder y-gate bank c x-decoder bank d x-decoder y-gate bank c address bank d address wp#/acc
september 22, 2006 S29PL-J_00_a9 S29PL-J 13 data sheet (advance information) 6. simultaneous read/write block diagram (pl129j) note amax = a21 (pl129j) v cc v ss bank 1a address bank 1b address a21?a0 reset# we# ce1# dq0?dq15 ce2# state control & command register ry/by# bank 1a x-decoder oe# dq15?dq0 status control a21?a0 a21?a0 a21?a0 a21?a0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 mux mux mux bank 1b x-decoder y-gate bank 2a x-decoder bank 2b x-decoder y-gate bank 2a address bank 2b address ce1#=l ce2#=h ce1#=h ce2#=l wp#/acc
14 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 7. connection diagrams 7.1 special package handling instructions 7.1.1 tsop, bga, pdip, ssop, and plcc packages special handling is required for flash memory products in molded packages. the package and/or data integrity may be compromised if the package body is expos ed to temperatures above 150c for prolonged periods of time. 7.1.2 fbga packages special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if t he package body is exposed to temperatures above 150c for prolonged periods of time. 7.2 80-ball fine-pitch bga?pl127j figure 7.1 80-ball fine-pitch bga, top view, balls facing down?pl127j b2 d2 e2 f2 g2 h2 j2 d3 e3 f3 g3 h3 j3 d4 e4 f4 g4 h4 j4 d5 e5 f5 g5 h5 j5 d6 e6 f6 g6 h6 j6 b7 d7 e7 f7 g7 h7 j7 nc dq15 a16 a15 a14 a12 a13 nc dq14 dq13 dq7 a11 a10 a8 a9 dq12 v cc dq5 a19 a21 reset# we# dq10 dq11 dq2 a20 a18 wp#/acc ry/by# dq8 dq9 dq0 a5 a6 a17 a7 ce# oe# k2 k3 k4 k5 k6 k7 v ss dq6 dq4 dq3 dq1 v ss a0 a1 a2 a4 a3 nc b1 d1 e1 f1 g1 h1 j1 v io nc nc nc nc nc nc nc a1 nc b8 d8 c2 c3 c4 c5 c6 c7 a2 a7 nc nc c1 c8 e8 f8 g8 h8 j8 nc nc k1 nc k8 nc l2 l7 nc nc m2 m7 nc nc l1 nc l8 nc m1 nc m8 nc v ss v io nc a22 nc nc a8 nc
september 22, 2006 S29PL-J_00_a9 S29PL-J 15 data sheet (advance information) 7.3 64-ball fine-pitch bg a?mcp compatible?pl127j figure 7.2 64-ball fine-pitch bga, mcp compatib le, top view, balls facing down?pl127j f7 f8 f9 g3 g4 g7 g8 g9 g2 h3 h4 h5 h6 h7 h8 h9 h2 nc nc b5 b6 c4 c5 c6 c7 c8 d2 d3 d4 d5 d6 d7 d8 d9 e2 e3 e4 e5 e6 e7 e8 e9 f2 f3 f4 j3 j4 j5 j6 j7 j8 j9 j2 k3 k4 k5 k6 k7 k8 l5 l6 nc nc c3 m1 m10 a1 a10 a5 a18 ry/by # a20 a9 a13 a21 a6 rfu reset# rfu a19 a12 a15 a7 rfu wp#/acc we# a8 a11 a2 a3 a22 a14 a10 a17 a4 a1 rfu dq15 dq13 dq4 dq3 dq9 oe# ce#f1 rfu rfu a16 rfu dq6 dq1 vss a0 vss dq7 dq12 rfu vccf dq10 dq0 rfu dq14 dq5 rfu dq11 dq2 dq8 rfu vccf
16 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 7.4 48-ball fine-pitch bga, pl064j and pl032j figure 7.3 48-ball fine-pitch bga, top view, ball s facing down?pl064j?pl032j: c4(a21)=nc b3 c3 d3 e3 f3 g3 h3 b4 c4 d4 e4 f4 g4 h4 b5 c5 d5 e5 f5 g5 h5 b6 c6 d6 e6 f6 g6 h6 v ss dq15 nc a16 a15 a14 a12 dq6 dq13 dq14 dq7 a11 a10 a8 dq4 v cc dq12 dq5 a19 a21 reset# dq3 dq11 dq10 dq2 a20 a18 wp#/acc a3 a4 a5 a6 a13 a9 we# ry/by# b2 c2 d2 e2 f2 g2 h2 dq1 dq9 dq8 dq0 a5 a6 a17 a2 a7 b1 c1 d1 e1 f1 g1 h1 v ss oe# ce# a0 a1 a2 a4 a1 a3
september 22, 2006 S29PL-J_00_a9 S29PL-J 17 data sheet (advance information) 7.5 56-pin tsop 20 x 14 mm figure 7.4 56-pin tsop 20 x 14 mm configuration?pl127j for this family of products, a single multi-chip compatib le package (tsop) is offered for each density to allow both standalone and multi-chip qualification using a singl e, adaptable package. this new methodology allows package standardization resulting in faster developmen t. the multi-chip compatible package includes all the pins required for standalone device operation and verification. in addition, extra pins are included for insertion of common data storage or logic devices to be used for multi-chip products. if a standalone device is required, the extra multi-chip specific pins are not connected and the standalone device operates normally. the multi- chip compatible package sizes were chosen to serve the largest number of combinations possible. there are only a few cases where a larger package size would be required to accommodate the multi-chip combination. this multi-chip compatible package set does not allo w for direct package migration from the am29bds128h, am29bds128g, am29bds640g products, which use legacy standalone packages. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 reset# ry/by# a0 a1 a2 a3 a4 a5 v cc dq0 dq1 dq2 dq3 v ssq dq4 dq5 dq6 dq7 v ss nc a6 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 wp#/acc we# nc a22 a21 a20 oe# nc ce# v ss dq15 dq14 dq13 dq12 v ssq v ccq dq11 dq10 dq9 dq8 v cc a19 23 24 25 26 27 28 a7 a8 a9 a10 a11 a12 34 33 32 31 30 29 a18 a17 a16 a15 a14 a13 v ccq
18 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 7.6 56-ball fine-pitch ball gr id array, pl064j and pl032j figure 7.5 56-ball fine-pitch bga, top view, ba lls facing down,?pl064j and pl032j, a7 a3 a2 dq8 dq14 rfu rfu wp/acc we# a8 a11 a2 a3 a4 a5 a6 a7 a6 rfu rst# rfu a19 a12 a15 b1 b2 b3 b4 b5 b6 b7 b8 a5 a18 ry/by# a20 a9 a13 a21 c1 c2 c3 c4 c5 c6 c7 c8 a1 a4 a17 a10 a14 rfu d1 d2 d3 d6 d7 d8 vss dq1 a0 dq6 rfu a16 e2 e3 e1 e6 e7 e8 ce1#f dq0 oe# dq9 dq3 dq4 dq13 dq15 rfu f1 f2 f3 f4 f5 f6 f7 f8 dq10 vccf rfu dq12 dq7 vss g1 g2 g3 g4 g5 g6 g7 g8 dq2 dq11 rfu dq5 h2 h7 h3 h4 h5 h6
september 22, 2006 S29PL-J_00_a9 S29PL-J 19 data sheet (advance information) 8. pin description note amax = a22 (pl127j), a21 (pl129j and pl064j), a20 (pl032j) 9. logic symbol amax?a0 address bus dq15?dq0 16-bit data inputs/outputs/float ce# chip enable inputs oe# output enable input we# write enable v ss device ground nc pin not connected internally ry/by# ready/busy output and open drain. when ry/by#= v ih , the device is ready to accept read operations and commands. when ry/ by#= v ol , the device is either executing an embedded algorithm or the device is executing a hardware reset operation. wp#/acc write protect/acceleration input. when wp#/acc= v il , the highest and lowest two 4k-word sect ors are write prot ected regardless of other sector protection c onfigurations. when wp#/acc= v ih , these sector are unprotected unless the dyb or ppb is programmed. when wp#/acc= 12v, program and erase operations are accelerated. v io input/output buffer power supply (1.65 v to 1.95 v (for pl127j and pl129j) or 2.7 v to 3.6 v (for all plxxxj devices)) v cc chip power supply (2.7 v to 3.6 v or 2.7 to 3.3 v) reset# hardware reset pin ce1#, ce2# chip enable inputs. ce1# controls the 64mb in banks 1a and 1b. ce2# controls the 64 mb in banks 2a and 2b. (only for pl129j) max+1 16 dq15?dq0 amax?a0 ce# oe# we# reset# ry/by# wp#/acc v io (v ccq )
20 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 10. device bus operations this section describes the requiremen ts and use of the device bus operati ons, which are initiated through the internal command register. the command register itse lf does not occupy any add ressable memory location. the register is a latch used to store the commands, along with the addr ess and data information needed to execute the command. the cont ents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. table 10.1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 8.5?9.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes 1. the sector protect and sector unprotect functions may also be implemented via programming equipment. see high voltage sector protection on page 48 . 2. wp#/acc must be high when writing to upper two and lower two sectors. 10.1 requirements for reading array data to read array data from the outputs, the system must drive the oe# and appropriate ce# pins (for pl129j - ce1#/ce2# pins) to v il . in pl129j, ce1# and ce2# are the power control and select the lower (ce1#) or upper (ce2#) halves of the device. ce# is the power c ontrol. oe# is the output c ontrol and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory cont ent occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. each bank remains enabled for read access until the command register contents are altered. refer to table 21.3 on page 84 for timing specifications and to figure 20.3 on page 74 for the timing diagram. i cc1 in the dc characteristics table represents th e active current specification for reading array data. table 10.1 pl127j device bus operations operation ce# oe# we# reset# wp#/acc addresses (amax?a0) dq15? dq0 read l l h h x a in d out write l h l h x (note 2) a in d in standby v io 0.3 v x x v io 0.3 v x (note 2) x high-z output disable l h h h x x high-z reset x x x l x x high-z temporary sector unprotect (high voltage) xxxv id xa in d in table 10.2 pl129j device bus operations operation ce1# ce2# oe# we# reset# wp#/acc addresses (a21?a0) dq15? dq0 read lh lh h x a in d out hl write lh hl h x (note 2) a in d in hl standby v io 0.3 v v io 0.3 v xx v io 0.3 v x x high-z output disable l l h h h x x high-z reset x x x x l x x high-z temporary sector unprotect (high voltage) xxxx v id xa in d in
september 22, 2006 S29PL-J_00_a9 S29PL-J 21 data sheet (advance information) 10.1.1 random read (non-page read) address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable addresses and stable ce# to valid data at the output inputs. the output enable access time is the delay from the falli ng edge of the oe# to valid data at the output inputs (assuming the addresses have been stable for at least t acc ?t oe time). 10.1.2 page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mode provides faster read access s peed for random locations within a page. address bits amax?a3 select an 8 word page, and address bits a2?a0 se lect a specific word within that page. this is an asynchronous operation with the microprocesso r supplying the specific word location. the random or initial page access is t acc or t ce and subsequent page read accesses (as long as the locations specified by the mi croprocessor falls within that page) is equivalent to t pac c . when ce# (ce1# and ce#2 in pl129j) is deasserted (=v ih ), the reassertion of ce# (ce1# or ce#2 in pl129j) for subsequent access has access time of t acc or t ce . here again, ce# (ce1# /ce#2 in pl129j)selects the device and oe# is the output control and should be used to gate data to the output inputs if the dev ice is selected. fast page mode accesses are obtained by keeping amax?a3 constant and changing a2?a0 to select the specific word within that page. 10.2 simultaneous read/write operation in addition to the conventional fe atures (read, program, erase-suspe nd read, erase-suspend program, and program-suspend read), the device is capable of readin g data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation). the bank can be selected by bank addresses (pl127j: a22?a20, pl12 9j and pl064j: a21?a19, pl032j: a20?a18) with zero latency. the simultaneous operation can execute mu lti-function mode in the same bank. table 10.3 page select word a2 a1 a0 word 0 0 0 0 word 1 0 0 1 word 2 0 1 0 word 3 0 1 1 word 4 1 0 0 word 5 1 0 1 word 6 1 1 0 word 7 1 1 1 table 10.4 bank select bank pl127j: a22?a20, pl064j: a21?a19, pl032j: a20?a18 bank a 000 bank b 001, 010, 011 bank c 100, 101, 110 bank d 111 bank ce1# ce2# pl129j: a21?a20 bank 1a 0 1 00 bank 1b 0 1 01, 10, 11 bank 2a 1 0 00, 01, 10 bank 2b 1 0 11
22 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 10.3 writing commands/command sequences to write a command or command sequence (which in cludes programming data to the device and erasing sectors of memory), the syste m must drive we# and ce# (ce1# or ce#2 in pl129j) to v il , and oe# to v ih . the device features an unlock bypass mode to facilitate faster progra mming. once a bank enters the unlock bypass mode, only two wr ite cycles are required to progr am a word, instead of four. word program command sequence on page 57 has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, mu ltiple sectors, or the entire device. table 10.4 on page 21 indicates the set of address space t hat each sector occupies. a ?bank address? is the set of address bits required to uniquely select a bank. similarly, a ?sector address? refers to the address bits required to uniquely select a sector. command definitions on page 55 has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. i cc2 in the dc characteristics table represents the active current specification for the write mode. see the timing specification tables and timing diagrams in section reset on page 75 for write operations. 10.3.1 accelerated program operation the device offers accelerated program operations thr ough the acc function. this function is primarily intended to allow faster manufactu ring throughput at the factory. if the system asserts v hh on this pin, the device automatically enters the aforementioned unlock bypass mode, temporarily unprotects any pr otected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system wo uld use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/acc pin returns the device to normal operation. note that v hh must not be asserted on wp#/acc fo r operations other than accelerated programming, or device damage may result. in addition, the wp#/acc pin should be raised to v cc when not in use. that is, the wp#/acc pin should not be left floating or unconnected; inco nsistent behavior of the device may result. 10.3.2 autoselect functions if the system writes the autosele ct command sequence, th e device enters the auto select mode. the system can then read autoselect codes from the internal regi ster (which is separate from the memory array) on dq15?dq0. standard read cycle timings apply in this mode. refer to the table 10.9, secured silicon sector addresses on page 39 and autoselect command sequence on page 56 for more information. 10.4 standby mode when the system is not reading or writing to the device , it can place the device in the standby mode. in this mode, current consumption is greatl y reduced, and the outputs are plac ed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# (ce1#,ce#2 in pl129j) and reset# pins are both held at v io 0.3 v. (note that this is a mo re restricted voltage range than v ih .) if ce# (ce1#,ce#2 in pl129j) and reset# are held at v ih , but not within v io 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of t hese standby modes, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. icc3 in dc characteristics on page 71 represents the cmos standby current specification.
september 22, 2006 S29PL-J_00_a9 S29PL-J 23 data sheet (advance information) 10.5 automatic sleep mode the automatic sleep mode minimizes flash device ener gy consumption. the devi ce automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals . standard address access timings pr ovide new data when addresses are changed. while in sleep mode, output data is latched and always availabl e to the system. note that during automatic sleep mode, oe# must be at v ih before the device reduces current to the stated sleep mode specification. icc5 in dc characteristics on page 71 represents the automatic sleep mode current specification. 10.6 reset#: hardware reset pin the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read /write commands for the durat ion of the reset# pulse. the device also resets the internal state machine to reading array data. the oper ation that was interrupted should be reinitiated once the device is ready to acc ept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (icc4). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset circuitry. a system rese t would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset# is asserted during a progra m or erase operation, the ry/by# pin remains a ?0? (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/by# to determine whet her the reset operation is complete. if reset# is asserted when a program or erase op eration is not executin g (ry/by# pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after the reset# pin returns to v ih . refer to the tables in ac characteristic on page 72 for reset# parameters and to figure 20.5 on page 75 for the timing diagram. 10.7 output disable mode when the oe# input is at v ih , output from the device is disabled. th e output pins (except for ry/by#) are placed in the highest impedance state table 10.5 pl127j sector architecture (sheet 1 of 7) bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank a sa0 00000000000 4 000000h?000fffh sa1 00000000001 4 001000h?001fffh sa2 00000000010 4 002000h?002fffh sa3 00000000011 4 003000h?003fffh sa4 00000000100 4 004000h?004fffh sa5 00000000101 4 005000h?005fffh sa6 00000000110 4 006000h?006fffh sa7 00000000111 4 007000h?007fffh sa8 00000001xxx 32 008000h?00ffffh sa9 00000010xxx 32 010000h?017fffh sa10 00000011xxx 32 018000h?01ffffh sa11 00000100xxx 32 020000h?027fffh sa12 00000101xxx 32 028000h?02ffffh sa13 00000110xxx 32 030000h?037fffh sa14 00000111xxx 32 038000h?03ffffh sa15 00001000xxx 32 040000h?047fffh sa16 00001001xxx 32 048000h?04ffffh
24 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) bank a sa17 00001010xxx 32 050000h?057fffh sa18 00001011xxx 32 058000h?05ffffh sa19 00001100xxx 32 060000h?067fffh sa20 00001101xxx 32 068000h?06ffffh sa21 00001110xxx 32 070000h?077fffh sa22 00001111xxx 32 078000h?07ffffh sa23 00010000xxx 32 080000h?087fffh sa24 00010001xxx 32 088000h?08ffffh sa25 00010010xxx 32 090000h?097fffh sa26 00010011xxx 32 098000h?09ffffh sa27 00010100xxx 32 0a0000h?0a7fffh sa28 00010101xxx 32 0a8000h?0affffh sa29 00010110xxx 32 0b0000h?0b7fffh sa30 00010111xxx 32 0b8000h?0bffffh sa31 00011000xxx 32 0c0000h?0c7fffh sa32 00011001xxx 32 0c8000h?0cffffh sa33 00011010xxx 32 0d0000h?0d7fffh sa34 00011011xxx 32 0d8000h?0dffffh sa35 00011100xxx 32 0e0000h?0e7fffh sa36 00011101xxx 32 0e8000h?0effffh sa37 00011110xxx 32 0f0000h?0f7fffh sa38 00011111xxx 32 0f8000h?0fffffh bank b sa39 00100000xxx 32 100000h?107fffh sa40 00100001xxx 32 108000h?10ffffh sa41 00100010xxx 32 110000h?117fffh sa42 00100011xxx 32 118000h?11ffffh sa43 00100100xxx 32 120000h?127fffh sa44 00100101xxx 32 128000h?12ffffh sa45 00100110xxx 32 130000h?137fffh sa46 00100111xxx 32 138000h?13ffffh sa47 00101000xxx 32 140000h?147fffh sa48 00101001xxx 32 148000h?14ffffh sa49 00101010xxx 32 150000h?157fffh sa50 00101011xxx 32 158000h?15ffffh sa51 00101100xxx 32 160000h?167fffh sa52 00101101xxx 32 168000h?16ffffh sa53 00101110xxx 32 170000h?177fffh sa54 00101111xxx 32 178000h?17ffffh sa55 00110000xxx 32 180000h?187fffh sa56 00110001xxx 32 188000h?18ffffh sa57 00110010xxx 32 190000h?197fffh sa58 00110011xxx 32 198000h?19ffffh sa59 00110100xxx 32 1a0000h?1a7fffh sa60 00110101xxx 32 1a8000h?1affffh sa61 00110110xxx 32 1b0000h?1b7fffh sa62 00110111xxx 32 1b8000h?1bffffh sa63 00111000xxx 32 1c0000h?1c7fffh sa64 00111001xxx 32 1c8000h?1cffffh sa65 00111010xxx 32 1d0000h?1d7fffh table 10.5 pl127j sector architecture (sheet 2 of 7) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
september 22, 2006 S29PL-J_00_a9 S29PL-J 25 data sheet (advance information) bank b sa66 00111011xxx 32 1d8000h?1dffffh sa67 00111100xxx 32 1e0000h?1e7fffh sa68 00111101xxx 32 1e8000h?1effffh sa69 00111110xxx 32 1f0000h?1f7fffh sa70 00111111xxx 32 1f8000h?1fffffh sa71 01000000xxx 32 200000h?207fffh sa72 01000001xxx 32 208000h?20ffffh sa73 01000010xxx 32 210000h?217fffh sa74 01000011xxx 32 218000h?21ffffh sa75 01000100xxx 32 220000h?227fffh sa76 01000101xxx 32 228000h?22ffffh sa77 01000110xxx 32 230000h?237fffh sa78 01000111xxx 32 238000h?23ffffh sa79 01001000xxx 32 240000h?247fffh sa80 01001001xxx 32 248000h?24ffffh sa81 01001010xxx 32 250000h?257fffh sa82 01001011xxx 32 258000h?25ffffh sa83 01001100xxx 32 260000h?267fffh sa84 01001101xxx 32 268000h?26ffffh sa85 01001110xxx 32 270000h?277fffh sa86 01001111xxx 32 278000h?27ffffh sa87 01010000xxx 32 280000h?287fffh sa88 01010001xxx 32 288000h?28ffffh sa89 01010010xxx 32 290000h?297fffh sa90 01010011xxx 32 298000h?29ffffh sa91 01010100xxx 32 2a0000h?2a7fffh sa92 01010101xxx 32 2a8000h?2affffh sa93 01010110xxx 32 2b0000h?2b7fffh sa94 01010111xxx 32 2b8000h?2bffffh sa95 01011000xxx 32 2c0000h?2c7fffh sa96 01011001xxx 32 2c8000h?2cffffh sa97 01011010xxx 32 2d0000h?2d7fffh sa98 01011011xxx 32 2d8000h?2dffffh sa99 01011100xxx 32 2e0000h?2e7fffh sa100 01011101xxx 32 2e8000h?2effffh sa101 01011110xxx 32 2f0000h?2f7fffh sa102 01011111xxx 32 2f8000h?2fffffh sa103 01100000xxx 32 300000h?307fffh sa104 01100001xxx 32 308000h?30ffffh sa105 01100010xxx 32 310000h?317fffh sa106 01100011xxx 32 318000h?31ffffh sa107 01100100xxx 32 320000h?327fffh sa108 01100101xxx 32 328000h?32ffffh sa109 01100110xxx 32 330000h?337fffh sa110 01100111xxx 32 338000h?33ffffh sa111 01101000xxx 32 340000h?347fffh sa112 01101001xxx 32 348000h?34ffffh sa113 01101010xxx 32 350000h?357fffh sa114 01101011xxx 32 358000h?35ffffh table 10.5 pl127j sector architecture (sheet 3 of 7) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
26 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) bank b sa115 01101100xxx 32 360000h?367fffh sa116 01101101xxx 32 368000h?36ffffh sa117 01101110xxx 32 370000h?377fffh sa118 01101111xxx 32 378000h?37ffffh sa119 01110000xxx 32 380000h?387fffh sa120 01110001xxx 32 388000h?38ffffh sa121 01110010xxx 32 390000h?397fffh sa122 01110011xxx 32 398000h?39ffffh sa123 01110100xxx 32 3a0000h?3a7fffh sa124 01110101xxx 32 3a8000h?3affffh sa125 01110110xxx 32 3b0000h?3b7fffh sa126 01110111xxx 32 3b8000h?3bffffh sa127 01111000xxx 32 3c0000h?3c7fffh sa128 01111001xxx 32 3c8000h?3cffffh sa129 01111010xxx 32 3d0000h?3d7fffh sa130 01111011xxx 32 3d8000h?3dffffh sa131 01111100xxx 32 3e0000h?3e7fffh sa132 01111101xxx 32 3e8000h?3effffh sa133 01111110xxx 32 3f0000h?3f7fffh sa134 01111111xxx 32 3f8000h?3fffffh bank c sa135 10000000xxx 32 400000h?407fffh sa136 10000001xxx 32 408000h?40ffffh sa137 10000010xxx 32 410000h?417fffh sa138 10000011xxx 32 418000h?41ffffh sa139 10000100xxx 32 420000h?427fffh sa140 10000101xxx 32 428000h?42ffffh sa141 10000110xxx 32 430000h?437fffh sa142 10000111xxx 32 438000h?43ffffh sa143 10001000xxx 32 440000h?447fffh sa144 10001001xxx 32 448000h?44ffffh sa145 10001010xxx 32 450000h?457fffh sa146 10001011xxx 32 458000h?45ffffh sa147 10001100xxx 32 460000h?467fffh sa148 10001101xxx 32 468000h?46ffffh sa149 10001110xxx 32 470000h?477fffh sa150 10001111xxx 32 478000h?47ffffh sa151 10010000xxx 32 480000h?487fffh sa152 10010001xxx 32 488000h?48ffffh sa153 10010010xxx 32 490000h?497fffh sa154 10010011xxx 32 498000h?49ffffh sa155 10010100xxx 32 4a0000h?4a7fffh sa156 10010101xxx 32 4a8000h?4affffh sa157 10010110xxx 32 4b0000h?4b7fffh sa158 10010111xxx 32 4b8000h?4bffffh sa159 10011000xxx 32 4c0000h?4c7fffh sa160 10011001xxx 32 4c8000h?4cffffh sa161 10011010xxx 32 4d0000h?4d7fffh sa162 10011011xxx 32 4d8000h?4dffffh sa163 10011100xxx 32 4e0000h?4e7fffh table 10.5 pl127j sector architecture (sheet 4 of 7) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
september 22, 2006 S29PL-J_00_a9 S29PL-J 27 data sheet (advance information) bank c sa164 10011101xxx 32 4e8000h?4effffh sa165 10011110xxx 32 4f0000h?4f7fffh sa166 10011111xxx 32 4f8000h?4fffffh sa167 10100000xxx 32 500000h?507fffh sa168 10100001xxx 32 508000h?50ffffh sa169 10100010xxx 32 510000h?517fffh sa170 10100011xxx 32 518000h?51ffffh sa171 10100100xxx 32 520000h?527fffh sa172 10100101xxx 32 528000h?52ffffh sa173 10100110xxx 32 530000h?537fffh sa174 10100111xxx 32 538000h?53ffffh sa175 10101000xxx 32 540000h?547fffh sa176 10101001xxx 32 548000h?54ffffh sa177 10101010xxx 32 550000h?557fffh sa178 10101011xxx 32 558000h?15ffffh sa179 10101100xxx 32 560000h?567fffh sa180 10101101xxx 32 568000h?56ffffh sa181 10101110xxx 32 570000h?577fffh sa182 10101111xxx 32 578000h?57ffffh sa183 10110000xxx 32 580000h?587fffh sa184 10110001xxx 32 588000h?58ffffh sa185 10110010xxx 32 590000h?597fffh sa186 10110011xxx 32 598000h?59ffffh sa187 10110100xxx 32 5a0000h?5a7fffh sa188 10110101xxx 32 5a8000h?5affffh sa189 10110110xxx 32 5b0000h?5b7fffh sa190 10110111xxx 32 5b8000h?5bffffh sa191 10111000xxx 32 5c0000h?5c7fffh sa192 10111001xxx 32 5c8000h?5cffffh sa193 10111010xxx 32 5d0000h?5d7fffh sa194 10111011xxx 32 5d8000h?5dffffh sa195 10111100xxx 32 5e0000h?5e7fffh sa196 10111101xxx 32 5e8000h?5effffh sa197 10111110xxx 32 5f0000h?5f7fffh sa198 10111111xxx 32 5f8000h?5fffffh sa199 11000000xxx 32 600000h?607fffh sa200 11000001xxx 32 608000h?60ffffh sa201 11000010xxx 32 610000h?617fffh sa202 11000011xxx 32 618000h?61ffffh sa203 11000100xxx 32 620000h?627fffh sa204 11000101xxx 32 628000h?62ffffh sa205 11000110xxx 32 630000h?637fffh sa206 11000111xxx 32 638000h?63ffffh sa207 11001000xxx 32 640000h?647fffh sa208 11001001xxx 32 648000h?64ffffh sa209 11001010xxx 32 650000h?657fffh sa210 11001011xxx 32 658000h?65ffffh sa211 11001100xxx 32 660000h?667fffh sa212 11001101xxx 32 668000h?66ffffh table 10.5 pl127j sector architecture (sheet 5 of 7) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
28 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) bank c sa213 11001110xxx 32 670000h?677fffh sa214 11001111xxx 32 678000h?67ffffh sa215 11010000xxx 32 680000h?687fffh sa216 11010001xxx 32 688000h?68ffffh sa217 11010010xxx 32 690000h?697fffh sa218 11010011xxx 32 698000h?69ffffh sa219 11010100xxx 32 6a0000h?6a7fffh sa220 11010101xxx 32 6a8000h?6affffh sa221 11010110xxx 32 6b0000h?6b7fffh sa222 11010111xxx 32 6b8000h?6bffffh sa223 11011000xxx 32 6c0000h?6c7fffh sa224 11011001xxx 32 6c8000h?6cffffh sa225 11011010xxx 32 6d0000h?6d7fffh sa226 11011011xxx 32 6d8000h?6dffffh sa227 11011100xxx 32 6e0000h?6e7fffh sa228 11011101xxx 32 6e8000h?6effffh sa229 11011110xxx 32 6f0000h?6f7fffh sa230 11011111xxx 32 6f8000h?6fffffh bank d sa231 11100000xxx 32 700000h?707fffh sa232 11100001xxx 32 708000h?70ffffh sa233 11100010xxx 32 710000h?717fffh sa234 11100011xxx 32 718000h?71ffffh sa235 11100100xxx 32 720000h?727fffh sa236 11100101xxx 32 728000h?72ffffh sa237 11100110xxx 32 730000h?737fffh sa238 11100111xxx 32 738000h?73ffffh sa239 11101000xxx 32 740000h?747fffh sa240 11101001xxx 32 748000h?74ffffh sa241 11101010xxx 32 750000h?757fffh sa242 11101011xxx 32 758000h?75ffffh sa243 11101100xxx 32 760000h?767fffh sa244 11101101xxx 32 768000h?76ffffh sa245 11101110xxx 32 770000h?777fffh sa246 11101111xxx 32 778000h?77ffffh sa247 11110000xxx 32 780000h?787fffh sa248 11110001xxx 32 788000h?78ffffh sa249 11110010xxx 32 790000h?797fffh sa250 11110011xxx 32 798000h?79ffffh sa251 11110100xxx 32 7a0000h?7a7fffh sa252 11110101xxx 32 7a8000h?7affffh sa253 11110110xxx 32 7b0000h?7b7fffh sa254 11110111xxx 32 7b8000h?7bffffh sa255 11111000xxx 32 7c0000h?7c7fffh sa256 11111001xxx 32 7c8000h?7cffffh sa257 11111010xxx 32 7d0000h?7d7fffh sa258 11111011xxx 32 7d8000h?7dffffh sa259 11111100xxx 32 7e0000h?7e7fffh sa260 11111101xxx 32 7e8000h?7effffh sa261 11111110xxx 32 7f0000h?7f7fffh table 10.5 pl127j sector architecture (sheet 6 of 7) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
september 22, 2006 S29PL-J_00_a9 S29PL-J 29 data sheet (advance information) bank d sa262 11111111000 4 7f8000h?7f8fffh sa263 11111111001 4 7f9000h?7f9fffh sa264 11111111010 4 7fa000h?7fafffh sa265 11111111011 4 7fb000h?7fbfffh sa266 11111111100 4 7fc000h?7fcfffh sa267 11111111101 4 7fd000h?7fdfffh sa268 11111111110 4 7fe000h?7fefffh sa269 11111111111 4 7ff000h?7fffffh table 10.6 pl064j sector architecture (sheet 1 of 4) bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank a sa0 0000000000 4 000000h?000fffh sa1 0000000001 4 001000h?001fffh sa2 0000000010 4 002000h?002fffh sa3 0000000011 4 003000h?003fffh sa4 0000000100 4 004000h?004fffh sa5 0000000101 4 005000h?005fffh sa6 0000000110 4 006000h?006fffh sa7 0000000111 4 007000h?007fffh sa8 0000001xxx 32 008000h?00ffffh sa9 0000010xxx 32 010000h?017fffh sa10 0000011xxx 32 018000h?01ffffh sa11 0000100xxx 32 020000h?027fffh sa12 0000101xxx 32 028000h?02ffffh sa13 0000110xxx 32 030000h?037fffh sa14 0000111xxx 32 038000h?03ffffh sa15 0001000xxx 32 040000h?047fffh sa16 0001001xxx 32 048000h?04ffffh sa17 0001010xxx 32 050000h?057fffh sa18 0001011xxx 32 058000h?05ffffh sa19 0001100xxx 32 060000h?067fffh sa20 0001101xxx 32 068000h?06ffffh sa21 0001110xxx 32 070000h?077fffh sa22 0001111xxx 32 078000h?07ffffh bank b sa23 0010000xxx 32 080000h?087fffh sa24 0010001xxx 32 088000h?08ffffh sa25 0010010xxx 32 090000h?097fffh sa26 0010011xxx 32 098000h?09ffffh sa27 0010100xxx 32 0a0000h?0a7fffh sa28 0010101xxx 32 0a8000h?0affffh sa29 0010110xxx 32 0b0000h?0b7fffh sa30 0010111xxx 32 0b8000h?0bffffh sa31 0011000xxx 32 0c0000h?0c7fffh sa32 0011001xxx 32 0c8000h?0cffffh sa33 0011010xxx 32 0d0000h?0d7fffh sa34 0011011xxx 32 0d8000h?0dffffh sa35 0011100xxx 32 0e0000h?0e7fffh sa36 0011101xxx 32 0e8000h?0effffh table 10.5 pl127j sector architecture (sheet 7 of 7) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
30 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) bank b sa37 0011110xxx 32 0f0000h?0f7fffh sa38 0011111xxx 32 0f8000h?0fffffh sa39 0100000xxx 32 100000h?107fffh sa40 0100001xxx 32 108000h?10ffffh sa41 0100010xxx 32 110000h?117fffh sa42 0100011xxx 32 118000h?11ffffh sa43 0100100xxx 32 120000h?127fffh sa44 0100101xxx 32 128000h?12ffffh sa45 0100110xxx 32 130000h?137fffh sa46 0100111xxx 32 138000h?13ffffh sa47 0101000xxx 32 140000h?147fffh sa48 0101001xxx 32 148000h?14ffffh sa49 0101010xxx 32 150000h?157fffh sa50 0101011xxx 32 158000h?15ffffh sa51 0101100xxx 32 160000h?167fffh sa52 0101101xxx 32 168000h?16ffffh sa53 0101110xxx 32 170000h?177fffh sa54 0101111xxx 32 178000h?17ffffh sa55 0110000xxx 32 180000h?187fffh sa56 0110001xxx 32 188000h?18ffffh sa57 0110010xxx 32 190000h?197fffh sa58 0110011xxx 32 198000h?19ffffh sa59 0110100xxx 32 1a0000h?1a7fffh sa60 0110101xxx 32 1a8000h?1affffh sa61 0110110xxx 32 1b0000h?1b7fffh sa62 0110111xxx 32 1b8000h?1bffffh sa63 0111000xxx 32 1c0000h?1c7fffh sa64 0111001xxx 32 1c8000h?1cffffh sa65 0111010xxx 32 1d0000h?1d7fffh sa66 0111011xxx 32 1d8000h?1dffffh sa67 0111100xxx 32 1e0000h?1e7fffh sa68 0111101xxx 32 1e8000h?1effffh sa69 0111110xxx 32 1f0000h?1f7fffh sa70 0111111xxx 32 1f8000h?1fffffh bank c sa71 1000000xxx 32 200000h?207fffh sa72 1000001xxx 32 208000h?20ffffh sa73 1000010xxx 32 210000h?217fffh sa74 1000011xxx 32 218000h?21ffffh sa75 1000100xxx 32 220000h?227fffh sa76 1000101xxx 32 228000h?22ffffh sa77 1000110xxx 32 230000h?237fffh sa78 1000111xxx 32 238000h?23ffffh sa79 1001000xxx 32 240000h?247fffh sa80 1001001xxx 32 248000h?24ffffh sa81 1001010xxx 32 250000h?257fffh sa82 1001011xxx 32 258000h?25ffffh sa83 1001100xxx 32 260000h?267fffh sa84 1001101xxx 32 268000h?26ffffh sa85 1001110xxx 32 270000h?277fffh table 10.6 pl064j sector architecture (sheet 2 of 4) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
september 22, 2006 S29PL-J_00_a9 S29PL-J 31 data sheet (advance information) bank c sa86 1001111xxx 32 278000h?27ffffh sa87 1010000xxx 32 280000h?287fffh sa88 1010001xxx 32 288000h?28ffffh sa89 1010010xxx 32 290000h?297fffh sa90 1010011xxx 32 298000h?29ffffh sa91 1010100xxx 32 2a0000h?2a7fffh sa92 1010101xxx 32 2a8000h?2affffh sa93 1010110xxx 32 2b0000h?2b7fffh sa94 1010111xxx 32 2b8000h?2bffffh sa95 1011000xxx 32 2c0000h?2c7fffh sa96 1011001xxx 32 2c8000h?2cffffh sa97 1011010xxx 32 2d0000h?2d7fffh sa98 1011011xxx 32 2d8000h?2dffffh sa99 1011100xxx 32 2e0000h?2e7fffh sa100 1011101xxx 32 2e8000h?2effffh sa101 1011110xxx 32 2f0000h?2f7fffh sa102 1011111xxx 32 2f8000h?2fffffh sa103 1100000xxx 32 300000h?307fffh sa104 1100001xxx 32 308000h?30ffffh sa105 1100010xxx 32 310000h?317fffh sa106 1100011xxx 32 318000h?31ffffh sa107 1100100xxx 32 320000h?327fffh sa108 1100101xxx 32 328000h?32ffffh sa109 1100110xxx 32 330000h?337fffh sa110 1100111xxx 32 338000h?33ffffh sa111 1101000xxx 32 340000h?347fffh sa112 1101001xxx 32 348000h?34ffffh sa113 1101010xxx 32 350000h?357fffh sa114 1101011xxx 32 358000h?35ffffh sa115 1101100xxx 32 360000h?367fffh sa116 1101101xxx 32 368000h?36ffffh sa117 1101110xxx 32 370000h?377fffh sa118 1101111xxx 32 378000h?37ffffh bank d sa119 1110000xxx 32 380000h?387fffh sa120 1110001xxx 32 388000h?38ffffh sa121 1110010xxx 32 390000h?397fffh sa122 1110011xxx 32 398000h?39ffffh sa123 1110100xxx 32 3a0000h?3a7fffh sa124 1110101xxx 32 3a8000h?3affffh sa125 1110110xxx 32 3b0000h?3b7fffh sa126 1110111xxx 32 3b8000h?3bffffh sa127 1111000xxx 32 3c0000h?3c7fffh sa128 1111001xxx 32 3c8000h?3cffffh sa129 1111010xxx 32 3d0000h?3d7fffh sa130 1111011xxx 32 3d8000h?3dffffh sa131 1111100xxx 32 3e0000h?3e7fffh sa132 1111101xxx 32 3e8000h?3effffh sa133 1111110xxx 32 3f0000h?3f7fffh sa134 1111111000 4 3f8000h?3f8fffh table 10.6 pl064j sector architecture (sheet 3 of 4) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
32 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) bank d sa135 1111111001 4 3f9000h?3f9fffh sa136 1111111010 4 3fa000h?3fafffh sa137 1111111011 4 3fb000h?3fbfffh sa138 1111111100 4 3fc000h?3fcfffh sa139 1111111101 4 3fd000h?3fdfffh sa140 1111111110 4 3fe000h?3fefffh sa141 1111111111 4 3ff000h?3fffffh table 10.7 pl032j sector architecture (sheet 1 of 2) bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank a sa0 000000000 4 000000h?000fffh sa1 000000001 4 001000h?001fffh sa2 000000010 4 002000h?002fffh sa3 000000011 4 003000h?003fffh sa4 000000100 4 004000h?004fffh sa5 000000101 4 005000h?005fffh sa6 000000110 4 006000h?006fffh sa7 000000111 4 007000h?007fffh sa8 000001xxx 32 008000h?00ffffh sa9 000010xxx 32 010000h?017fffh sa10 000011xxx 32 018000h?01ffffh sa11 000100xxx 32 020000h?027fffh sa12 000101xxx 32 028000h?02ffffh sa13 000110xxx 32 030000h?037fffh sa14 000111xxx 32 038000h?03ffffh bank b sa15 001000xxx 32 040000h?047fffh sa16 001001xxx 32 048000h?04ffffh sa17 001010xxx 32 050000h?057fffh sa18 001011xxx 32 058000h?05ffffh sa19 001100xxx 32 060000h?067fffh sa20 001101xxx 32 068000h?06ffffh sa21 001110xxx 32 070000h?077fffh sa22 001111xxx 32 078000h?07ffffh sa23 010000xxx 32 080000h?087fffh sa24 010001xxx 32 088000h?08ffffh sa25 010010xxx 32 090000h?097fffh sa26 010011xxx 32 098000h?09ffffh sa27 010100xxx 32 0a0000h?0a7fffh sa28 010101xxx 32 0a8000h?0affffh sa29 010110xxx 32 0b0000h?0b7fffh sa30 010111xxx 32 0b8000h?0bffffh sa31 011000xxx 32 0c0000h?0c7fffh sa32 011001xxx 32 0c8000h?0cffffh sa33 011010xxx 32 0d0000h?0d7fffh sa34 011011xxx 32 0d8000h?0dffffh sa35 011100xxx 32 0e0000h?0e7fffh sa36 011101xxx 32 0e8000h?0effffh sa37 011110xxx 32 0f0000h?0f7fffh table 10.6 pl064j sector architecture (sheet 4 of 4) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
september 22, 2006 S29PL-J_00_a9 S29PL-J 33 data sheet (advance information) bank b sa38 011111xxx 32 0f8000h?0fffffh bank c sa39 100000xxx 32 100000h?107fffh sa40 100001xxx 32 108000h?10ffffh sa41 100010xxx 32 110000h?117fffh sa42 100011xxx 32 118000h?11ffffh sa43 100100xxx 32 120000h?127fffh sa44 100101xxx 32 128000h?12ffffh sa45 100110xxx 32 130000h?137fffh sa46 100111xxx 32 138000h?13ffffh sa47 101000xxx 32 140000h?147fffh sa48 101001xxx 32 148000h?14ffffh sa49 101010xxx 32 150000h?157fffh sa50 101011xxx 32 158000h?15ffffh sa51 101100xxx 32 160000h?167fffh sa52 101101xxx 32 168000h?16ffffh sa53 101110xxx 32 170000h?177fffh sa54 101111xxx 32 178000h?17ffffh sa55 110000xxx 32 180000h?187fffh sa56 110001xxx 32 188000h?18ffffh sa57 110010xxx 32 190000h?197fffh sa58 110011xxx 32 198000h?19ffffh sa59 110100xxx 32 1a0000h?1a7fffh sa60 110101xxx 32 1a8000h?1affffh sa61 110110xxx 32 1b0000h?1b7fffh sa62 110111xxx 32 1b8000h?1bffffh bank d sa63 111000xxx 32 1c0000h?1c7fffh sa64 111001xxx 32 1c8000h?1cffffh sa65 111010xxx 32 1d0000h?1d7fffh sa66 111011xxx 32 1d8000h?1dffffh sa67 111100xxx 32 1e0000h?1e7fffh sa68 111101xxx 32 1e8000h?1effffh sa69 111110xxx 32 1f0000h?1f7fffh sa70 111111000 4 1f8000h?1f8fffh sa71 111111001 4 1f9000h?1f9fffh sa72 111111010 4 1fa000h?1fafffh sa73 111111011 4 1fb000h?1fbfffh sa74 111111100 4 1fc000h?1fcfffh sa75 111111101 4 1fd000h?1fdfffh sa76 111111110 4 1fe000h?1fefffh sa77 111111111 4 1ff000h?1fffffh table 10.7 pl032j sector architecture (sheet 2 of 2) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
34 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) table 10.8 s29pl129j sector architecture (sheet 1 of 6) bank sector ce1# ce2# sector address (a21-a12) sector size (kwords) address range (x16) bank 1a sa1-0 0 1 0000000000 4 000000h?000fffh sa1-1 0 1 0000000001 4 001000h?001fffh sa1-2 0 1 0000000010 4 002000h?002fffh sa1-3 0 1 0000000011 4 003000h?003fffh sa1-4 0 1 0000000100 4 004000h?004fffh sa1-5 0 1 0000000101 4 005000h?005fffh sa1-6 0 1 0000000110 4 006000h?006fffh sa1-7 0 1 0000000111 4 007000h?007fffh sa1-8 0 1 0000001xxx 32 008000h?00ffffh sa1-9 0 1 0000010xxx 32 010000h?017fffh sa1-10 0 1 0000011xxx 32 018000h?01ffffh sa1-11 0 1 0000100xxx 32 020000h?027fffh sa1-12 0 1 0000101xxx 32 028000h?02ffffh sa1-13 0 1 0000110xxx 32 030000h?037fffh sa1-14 0 1 0000111xxx 32 038000h?03ffffh sa1-15 0 1 0001000xxx 32 040000h?047fffh sa1-16 0 1 0001001xxx 32 048000h?04ffffh sa1-17 0 1 0001010xxx 32 050000h?057fffh sa1-18 0 1 0001011xxx 32 058000h?05ffffh sa1-19 0 1 0001100xxx 32 060000h?067fffh sa1-20 0 1 0001101xxx 32 068000h?06ffffh sa1-21 0 1 0001110xxx 32 070000h?077fffh sa1-22 0 1 0001111xxx 32 078000h?07ffffh sa1-23 0 1 0010000xxx 32 080000h?087fffh sa1-24 0 1 0010001xxx 32 088000h?08ffffh sa1-25 0 1 0010010xxx 32 090000h?097fffh sa1-26 0 1 0010011xxx 32 098000h?09ffffh sa1-27 0 1 0010100xxx 32 0a0000h?0a7fffh sa1-28 0 1 0010101xxx 32 0a8000h?0affffh sa1-29 0 1 0010110xxx 32 0b0000h?0b7fffh sa1-30 0 1 0010111xxx 32 0b8000h?0bffffh sa1-31 0 1 0011000xxx 32 0c0000h?0c7fffh sa1-32 0 1 0011001xxx 32 0c8000h?0cffffh sa1-33 0 1 0011010xxx 32 0d0000h?0d7fffh sa1-34 0 1 0011011xxx 32 0d8000h?0dffffh sa1-35 0 1 0011100xxx 32 0e0000h?0e7fffh sa1-36 0 1 0011101xxx 32 0e8000h?0effffh sa1-37 0 1 0011110xxx 32 0f0000h?0f7fffh sa1-38 0 1 0011111xxx 32 0f8000h?0fffffh bank 1b sa1-39 0 1 0100000xxx 32 100000h?107fffh sa1-40 0 1 0100001xxx 32 108000h?10ffffh sa1-41 0 1 0100010xxx 32 110000h?117fffh sa1-42 0 1 0100011xxx 32 118000h?11ffffh sa1-43 0 1 0100100xxx 32 120000h?127fffh sa1-44 0 1 0100101xxx 32 128000h?12ffffh sa1-45 0 1 0100110xxx 32 130000h?137fffh sa1-46 0 1 0100111xxx 32 138000h?13ffffh sa1-47 0 1 0101000xxx 32 140000h?147fffh
september 22, 2006 S29PL-J_00_a9 S29PL-J 35 data sheet (advance information) bank 1b sa1-48 0 1 0101001xxx 32 148000h?14ffffh sa1-49 0 1 0101010xxx 32 150000h?157fffh sa1-50 0 1 0101011xxx 32 158000h?15ffffh sa1-51 0 1 0101100xxx 32 160000h?167fffh sa1-52 0 1 0101101xxx 32 168000h?16ffffh sa1-53 0 1 0101110xxx 32 170000h?177fffh sa1-54 0 1 0101111xxx 32 178000h?17ffffh sa1-55 0 1 0110000xxx 32 180000h?187fffh sa1-56 0 1 0110001xxx 32 188000h?18ffffh sa1-57 0 1 0110010xxx 32 190000h?197fffh sa1-58 0 1 0110011xxx 32 198000h?19ffffh sa1-59 0 1 0110100xxx 32 1a0000h?1a7fffh sa1-60 0 1 0110101xxx 32 1a8000h?1affffh sa1-61 0 1 0110110xxx 32 1b0000h?1b7fffh sa1-62 0 1 0110111xxx 32 1b8000h?1bffffh sa1-63 0 1 0111000xxx 32 1c0000h?1c7fffh sa1-64 0 1 0111001xxx 32 1c8000h?1cffffh sa1-65 0 1 0111010xxx 32 1d0000h?1d7fffh sa1-66 0 1 0111011xxx 32 1d8000h?1dffffh sa1-67 0 1 0111100xxx 32 1e0000h?1e7fffh sa1-68 0 1 0111101xxx 32 1e8000h?1effffh sa1-69 0 1 0111110xxx 32 1f0000h?1f7fffh sa1-70 0 1 0111111xxx 32 1f8000h?1fffffh sa1-71 0 1 1000000xxx 32 200000h?207fffh sa1-72 0 1 1000001xxx 32 208000h?20ffffh sa1-73 0 1 1000010xxx 32 210000h?217fffh sa1-74 0 1 1000011xxx 32 218000h?21ffffh sa1-75 0 1 1000100xxx 32 220000h?227fffh sa1-76 0 1 1000101xxx 32 228000h?22ffffh sa1-77 0 1 1000110xxx 32 230000h?237fffh sa1-78 0 1 1000111xxx 32 238000h?23ffffh sa1-79 0 1 1001000xxx 32 240000h?247fffh sa1-80 0 1 1001001xxx 32 248000h?24ffffh sa1-81 0 1 1001010xxx 32 250000h?257fffh sa1-82 0 1 1001011xxx 32 258000h?25ffffh sa1-83 0 1 1001100xxx 32 260000h?267fffh sa1-84 0 1 1001101xxx 32 268000h?26ffffh sa1-85 0 1 1001110xxx 32 270000h?277fffh sa1-86 0 1 1001111xxx 32 278000h?27ffffh sa1-87 0 1 1010000xxx 32 280000h?287fffh sa1-88 0 1 1010001xxx 32 288000h?28ffffh sa1-89 0 1 1010010xxx 32 290000h?297fffh sa1-90 0 1 1010011xxx 32 298000h?29ffffh sa1-91 0 1 1010100xxx 32 2a0000h?2a7fffh sa1-92 0 1 1010101xxx 32 2a8000h?2affffh sa1-93 0 1 1010110xxx 32 2b0000h?2b7fffh sa1-94 0 1 1010111xxx 32 2b8000h?2bffffh sa1-95 0 1 1011000xxx 32 2c0000h?2c7fffh sa1-96 0 1 1011001xxx 32 2c8000h?2cffffh table 10.8 s29pl129j sector architecture (sheet 2 of 6) bank sector ce1# ce2# sector address (a21-a12) sector size (kwords) address range (x16)
36 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) bank 1b sa1-97 0 1 1011010xxx 32 2d0000h?2d7fffh sa1-98 0 1 1011011xxx 32 2d8000h?2dffffh sa1-99 0 1 1011100xxx 32 2e0000h?2e7fffh sa1-100 0 1 1011101xxx 32 2e8000h?2effffh sa1-101 0 1 1011110xxx 32 2f0000h?2f7fffh sa1-102 0 1 1011111xxx 32 2f8000h?2fffffh sa1-103 0 1 1100000xxx 32 300000h?307fffh sa1-104 0 1 1100001xxx 32 308000h?30ffffh sa1-105 0 1 1100010xxx 32 310000h?317fffh sa1-106 0 1 1100011xxx 32 318000h?31ffffh sa1-107 0 1 1100100xxx 32 320000h?327fffh sa1-108 0 1 1100101xxx 32 328000h?32ffffh sa1-109 0 1 1100110xxx 32 330000h?337fffh sa1-110 0 1 1100111xxx 32 338000h?33ffffh sa1-111 0 1 1101000xxx 32 340000h?347fffh sa1-112 0 1 1101001xxx 32 348000h?34ffffh sa1-113 0 1 1101010xxx 32 350000h?357fffh sa1-114 0 1 1101011xxx 32 358000h?35ffffh sa1-115 0 1 1101100xxx 32 360000h?367fffh sa1-116 0 1 1101101xxx 32 368000h?36ffffh sa1-117 0 1 1101110xxx 32 370000h?377fffh sa1-118 0 1 1101111xxx 32 378000h?37ffffh sa1-119 0 1 1110000xxx 32 380000h?387fffh sa1-120 0 1 1110001xxx 32 388000h?38ffffh sa1-121 0 1 1110010xxx 32 390000h?397fffh sa1-122 0 1 1110011xxx 32 398000h?39ffffh sa1-123 0 1 1110100xxx 32 3a0000h?3a7fffh sa1-124 0 1 1110101xxx 32 3a8000h?3affffh sa1-125 0 1 1110110xxx 32 3b0000h?3b7fffh sa1-126 0 1 1110111xxx 32 3b8000h?3bffffh sa1-127 0 1 1111000xxx 32 3c0000h?3c7fffh sa1-128 0 1 1111001xxx 32 3c8000h?3cffffh sa1-129 0 1 1111010xxx 32 3d0000h?3d7fffh sa1-130 0 1 1111011xxx 32 3d8000h?3dffffh sa1-131 0 1 1111100xxx 32 3e0000h?3e7fffh sa1-132 0 1 1111101xxx 32 3e8000h?3effffh sa1-133 0 1 1111110xxx 32 3f0000h?3f7fffh sa1-134 0 1 1111111xxx 32 3f8000h?3fffffh bank 2a sa2-0 1 0 0000000xxx 32 000000h?007fffh sa2-1 1 0 0000001xxx 32 008000h?00ffffh sa2-2 1 0 0000010xxx 32 010000h?017fffh sa2-3 1 0 0000011xxx 32 018000h?01ffffh sa2-4 1 0 0000100xxx 32 020000h?027fffh sa2-5 1 0 0000101xxx 32 028000h?02ffffh sa2-6 1 0 0000110xxx 32 030000h?037fffh sa2-7 1 0 0000111xxx 32 038000h?03ffffh sa2-8 1 0 0001000xxx 32 040000h?047fffh sa2-9 1 0 0001001xxx 32 048000h?04ffffh sa2-10 1 0 0001010xxx 32 050000h?057fffh table 10.8 s29pl129j sector architecture (sheet 3 of 6) bank sector ce1# ce2# sector address (a21-a12) sector size (kwords) address range (x16)
september 22, 2006 S29PL-J_00_a9 S29PL-J 37 data sheet (advance information) bank 2a sa2-11 1 0 0001011xxx 32 058000h?05ffffh sa2-12 1 0 0001100xxx 32 060000h?067fffh sa2-13 1 0 0001101xxx 32 068000h?06ffffh sa2-14 1 0 0001110xxx 32 070000h?077fffh sa2-15 1 0 0001111xxx 32 078000h?07ffffh sa2-16 1 0 0010000xxx 32 080000h?087fffh sa2-17 1 0 0010001xxx 32 088000h?08ffffh sa2-18 1 0 0010010xxx 32 090000h?097fffh sa2-19 1 0 0010011xxx 32 098000h?09ffffh sa2-20 1 0 0010100xxx 32 0a0000h?0a7fffh sa2-21 1 0 0010101xxx 32 0a8000h?0affffh sa2-22 1 0 0010110xxx 32 0b0000h?0b7fffh sa2-23 1 0 0010111xxx 32 0b8000h?0bffffh sa2-24 1 0 0011000xxx 32 0c0000h?0c7fffh sa2-25 1 0 0011001xxx 32 0c8000h?0cffffh sa2-26 1 0 0011010xxx 32 0d0000h?0d7fffh sa2-27 1 0 0011011xxx 32 0d8000h?0dffffh sa2-28 1 0 0011100xxx 32 0e0000h?0e7fffh sa2-29 1 0 0011101xxx 32 0e8000h?0effffh sa2-30 1 0 0011110xxx 32 0f0000h?0f7fffh sa2-31 1 0 0011111xxx 32 0f8000h?0fffffh sa2-32 1 0 0100000xxx 32 100000h?107fffh sa2-33 1 0 0100001xxx 32 108000h?10ffffh sa2-34 1 0 0100010xxx 32 110000h?117fffh sa2-35 1 0 0100011xxx 32 118000h?11ffffh sa2-36 1 0 0100100xxx 32 120000h?127fffh sa2-37 1 0 0100101xxx 32 128000h?12ffffh sa2-38 1 0 0100110xxx 32 130000h?137fffh sa2-39 1 0 0100111xxx 32 138000h?13ffffh sa2-40 1 0 0101000xxx 32 140000h?147fffh sa2-41 1 0 0101001xxx 32 148000h?14ffffh sa2-42 1 0 0101010xxx 32 150000h?157fffh sa2-43 1 0 0101011xxx 32 158000h?15ffffh sa2-44 1 0 0101100xxx 32 160000h?167fffh sa2-45 1 0 0101101xxx 32 168000h?16ffffh sa2-46 1 0 0101110xxx 32 170000h?177fffh sa2-47 1 0 0101111xxx 32 178000h?17ffffh sa2-48 1 0 0110000xxx 32 180000h?187fffh sa2-49 1 0 0110001xxx 32 188000h?18ffffh sa2-50 1 0 0110010xxx 32 190000h?197fffh sa2-51 1 0 0110011xxx 32 198000h?19ffffh sa2-52 1 0 0110100xxx 32 1a0000h?1a7fffh sa2-53 1 0 0110101xxx 32 1a8000h?1affffh sa2-54 1 0 0110110xxx 32 1b0000h?1b7fffh sa2-55 1 0 0110111xxx 32 1b8000h?1bffffh sa2-56 1 0 0111000xxx 32 1c0000h?1c7fffh sa2-57 1 0 0111001xxx 32 1c8000h?1cffffh sa2-58 1 0 0111010xxx 32 1d0000h?1d7fffh sa2-59 1 0 0111011xxx 32 1d8000h?1dffffh table 10.8 s29pl129j sector architecture (sheet 4 of 6) bank sector ce1# ce2# sector address (a21-a12) sector size (kwords) address range (x16)
38 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) bank 2a sa2-60 1 0 0111100xxx 32 1e0000h?1e7fffh sa2-61 1 0 0111101xxx 32 1e8000h?1effffh sa2-62 1 0 0111110xxx 32 1f0000h?1f7fffh sa2-63 1 0 0111111xxx 32 1f8000h?1fffffh sa2-64 1 0 1000000xxx 32 200000h?207fffh sa2-65 1 0 1000001xxx 32 208000h?20ffffh sa2-66 1 0 1000010xxx 32 210000h?217fffh sa2-67 1 0 1000011xxx 32 218000h?21ffffh sa2-68 1 0 1000100xxx 32 220000h?227fffh sa2-69 1 0 1000101xxx 32 228000h?22ffffh sa2-70 1 0 1000110xxx 32 230000h?237fffh sa2-71 1 0 1000111xxx 32 238000h?23ffffh sa2-72 1 0 1001000xxx 32 240000h?247fffh sa2-73 1 0 1001001xxx 32 248000h?24ffffh sa2-74 1 0 1001010xxx 32 250000h?257fffh sa2-75 1 0 1001011xxx 32 258000h?25ffffh sa2-76 1 0 1001100xxx 32 260000h?267fffh sa2-77 1 0 1001101xxx 32 268000h?26ffffh sa2-78 1 0 1001110xxx 32 270000h?277fffh sa2-79 1 0 1001111xxx 32 278000h?27ffffh sa2-80 1 0 1010000xxx 32 280000h?287fffh sa2-81 1 0 1010001xxx 32 288000h?28ffffh sa2-82 1 0 1010010xxx 32 290000h?297fffh sa2-83 1 0 1010011xxx 32 298000h?29ffffh sa2-84 1 0 1010100xxx 32 2a0000h?2a7fffh sa2-85 1 0 1010101xxx 32 2a8000h?2affffh sa2-86 1 0 1010110xxx 32 2b0000h?2b7fffh sa2-87 1 0 1010111xxx 32 2b8000h?2bffffh sa2-88 1 0 1011000xxx 32 2c0000h?2c7fffh sa2-89 1 0 1011001xxx 32 2c8000h?2cffffh sa2-90 1 0 1011010xxx 32 2d0000h?2d7fffh sa2-91 1 0 1011011xxx 32 2d8000h?2dffffh sa2-92 1 0 1011100xxx 32 2e0000h?2e7fffh sa2-93 1 0 1011101xxx 32 2e8000h?2effffh sa2-94 1 0 1011110xxx 32 2f0000h?2f7fffh sa2-95 1 0 1011111xxx 32 2f8000h?2fffffh bank 2b sa2-96 1 0 1100000xxx 32 300000h?307fffh sa2-97 1 0 1100001xxx 32 308000h?30ffffh sa2-98 1 0 1100010xxx 32 310000h?317fffh sa2-99 1 0 1100011xxx 32 318000h?31ffffh sa2-100 1 0 1100100xxx 32 320000h?327fffh sa2-101 1 0 1100101xxx 32 328000h?32ffffh sa2-102 1 0 1100110xxx 32 330000h?337fffh sa2-103 1 0 1100111xxx 32 338000h?33ffffh sa2-104 1 0 1101000xxx 32 340000h?347fffh sa2-105 1 0 1101001xxx 32 348000h?34ffffh sa2-106 1 0 1101010xxx 32 350000h?357fffh sa2-107 1 0 1101011xxx 32 358000h?35ffffh sa2-108 1 0 1101100xxx 32 360000h?367fffh table 10.8 s29pl129j sector architecture (sheet 5 of 6) bank sector ce1# ce2# sector address (a21-a12) sector size (kwords) address range (x16)
september 22, 2006 S29PL-J_00_a9 S29PL-J 39 data sheet (advance information) 10.8 autoselect mode the autoselect mode provides manufa cturer and device identification, an d sector protection verification, through identifier codes output on dq7?dq0. this mo de is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through th e command register. when using programming equipment, the autoselect mode requires v id on address pin a9. address pins must be as shown in table 10.10 on page 40 and table 10.11 on page 40 . in addition, when verifying sector protection, the sector address must appear on t he appropriate highest order address bits (see table 10.4 on page 21 ). table 10.10 and table 10.11 show the remaining address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq 7?dq0. however, the autoselect codes can al so be accessed in-system through the command register, for instances when the device is erased or programmed in a system without access to high voltage on the a9 pin. the co mmand sequence is illustrated in table 15.1 on page 62 . note that if a bank address (ba) (on address bits pl127j: a22 ? a20, pl129j and pl064j: a21 ? a19, pl032j: a20 ?a18) is asserted during the thir d write cycle of the autosel ect command, the host system can read autoselect data that bank and then immediately read array data fr om the other bank, without exiting the autoselect mode. bank 2b sa2-109 1 0 1101101xxx 32 368000h?36ffffh sa2-110 1 0 1101110xxx 32 370000h?377fffh sa2-111 1 0 1101111xxx 32 378000h?37ffffh sa2-112 1 0 1110000xxx 32 380000h?387fffh sa2-113 1 0 1110001xxx 32 388000h?38ffffh sa2-114 1 0 1110010xxx 32 390000h?397fffh sa2-115 1 0 1110011xxx 32 398000h?39ffffh sa2-116 1 0 1110100xxx 32 3a0000h?3a7fffh sa2-117 1 0 1110101xxx 32 3a8000h?3affffh sa2-118 1 0 1110110xxx 32 3b0000h?3b7fffh sa2-119 1 0 1110111xxx 32 3b8000h?3bffffh sa2-120 1 0 1111000xxx 32 3c0000h?3c7fffh sa2-121 1 0 1111001xxx 32 3c8000h?3cffffh sa2-122 1 0 1111010xxx 32 3d0000h?3d7fffh sa2-123 1 0 1111011xxx 32 3d8000h?3dffffh sa2-124 1 0 1111100xxx 32 3e0000h?3e7fffh sa2-125 1 0 1111101xxx 32 3e8000h?3effffh sa2-126 1 0 1111110xxx 32 3f0000h?3f7fffh sa2-127 1 0 1111111000 4 3f8000h?3f8fffh sa2-128 1 0 1111111001 4 3f9000h?3f9fffh sa2-129 1 0 1111111010 4 3fa000h?3fafffh sa2-130 1 0 1111111011 4 3fb000h?3fbfffh sa2-131 1 0 1111111100 4 3fc000h?3fcfffh sa2-132 1 0 1111111101 4 3fd000h?3fdfffh sa2-133 1 0 1111111110 4 3fe000h?3fefffh sa2-134 1 0 1111111111 4 3ff000h?3fffffh table 10.9 secured silicon sector addresses sector size address range factory-locked area 64 words 000000h-00003fh customer-lockable area 64 words 000040h-00007fh table 10.8 s29pl129j sector architecture (sheet 6 of 6) bank sector ce1# ce2# sector address (a21-a12) sector size (kwords) address range (x16)
40 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) to access the autoselect codes in-system, the hos t system can issue the aut oselect command via the command register, as shown in table 15.1 on page 62 . this method does not require v id . refer to the autoselect command sequence on page 56 for more information. legend l = logic low = v il , h = logic high = v ih , ba = bank address, sa = sector address, x = don?t care. note when polling the secured silicon indicator bit the bank address (ba) should be set within the address range 004000h-03ffffh. legend l = logic low = v il , h = logic high = v ih , ba = bank address, sa = sector address, x = don?t care. note 1. when polling the secured silicon indicator bit the a21 to a12 should be set within the address range 004000h-03ffffh. 2. the autoselect codes may also be access ed in-system by using the command sequences table 10.10 autoselect codes (high voltage method) description ce# oe# we# amax to a12 a10 a9 a8 a7 a6 a5 to a4 a3 a2 a1 a0 dq15 to dq0 manufacturer id : spansion products ll h ba x v i d xll x llll0 001h device id read cycle 1 l lh ba x v i d xll l lllh227eh read cycle 2 l h h h l 2220h (pl127j) 2202h (pl064j) 220ah (pl032j) read cycle 3 l h h h h 2200h (pl127j) 2201h (pl064j) 2201h (pl032j) sector protection ver ification ll h sa x v i d xll l llhl 0001h (protected), 0000h (unprotected) secured silicon indicator bit (dq7, dq6) ll h ba (see note) x v i d xxl x l lhh dq7=1 (factory locked), dq6=1 (factory and customer locked) table 10.11 autoselect codes for pl129j description ce1# ce2# oe# we# a21 to a12 a10 a9 a8 a7 a6 a5 to a4 a3 a2 a1 a0 dq15 to dq0 manufacturer id : spansion products lh lh x x v i d x l l x l l l l 0001h hl device id read cycle 1 lh lh x x v i d xlll lllh227eh hl read cycle 2 lh h h h l 2221h hl read cycle 3 lh h h h h 2200h hl sector protection ver ification lh lh sa x v i d xlllllhl 0001h (protected), 0000h (unprotected) hl secured silicon indicator bit (dq7, dq6) lh lh x (note 1) x v i d xxlxl lhh dq7=1 (factory locked), dq6=1 (factory and customer locked) hl
september 22, 2006 S29PL-J_00_a9 S29PL-J 41 data sheet (advance information) table 10.12 pl127j boot sector/sector block addresses for protection/unprotection sector a22-a12 sector/ sector block size sector a22-a12 sector/ sector block size sa0 00000000000 4 kwords sa131-sa134 011111xxxxx 128 (4x32) kwords sa1 00000000001 4 kwords sa135-sa138 100000xxxxx 128 (4x32) kwords sa2 00000000010 4 kwords sa139-sa142 100001xxxxx 128 (4x32) kwords sa3 00000000011 4 kwords sa143-sa146 100010xxxxx 128 (4x32) kwords sa4 00000000100 4 kwords sa147-sa150 100011xxxxx 128 (4x32) kwords sa5 00000000101 4 kwords sa151-sa154 100100xxxxx 128 (4x32) kwords sa6 00000000110 4 kwords sa155-sa158 100101xxxxx 128 (4x32) kwords sa7 00000000111 4 kwords sa159-sa162 100110xxxxx 128 (4x32) kwords sa8 00000001xxx 32 kwords sa163-sa166 100111xxxxx 128 (4x32) kwords sa9 00000010xxx 32 kwords sa167-sa170 101000xxxxx 128 (4x32) kwords sa10 00000011xxx 32 kwords sa171-sa174 101001xxxxx 128 (4x32) kwords sa11-sa14 000001xxxxx 128 (4x32) kwords sa175-sa178 101010xxxxx 128 (4x32) kwords sa15-sa18 000010xxxxx 128 (4x32) kwords sa179-sa182 101011xxxxx 128 (4x32) kwords sa19-sa22 000011xxxxx 128 (4x32) kwords sa183-sa186 101100xxxxx 128 (4x32) kwords sa23-sa26 000100xxxxx 128 (4x32) kwords sa187-sa190 101101xxxxx 128 (4x32) kwords sa27-sa30 000101xxxxx 128 (4x32) kwords sa191-sa194 101110xxxxx 128 (4x32) kwords sa31-sa34 000110xxxxx 128 (4x32) kwords sa195-sa198 101111xxxxx 128 (4x32) kwords sa35-sa38 000111xxxxx 128 (4x32) kwords sa199-sa202 110000xxxxx 128 (4x32) kwords sa39-sa42 001000xxxxx 128 (4x32) kwords sa203-sa206 110001xxxxx 128 (4x32) kwords sa43-sa46 001001xxxxx 128 (4x32) kwords sa207-sa210 110010xxxxx 128 (4x32) kwords sa47-sa50 001010xxxxx 128 (4x32) kwords sa211-sa214 110011xxxxx 128 (4x32) kwords sa51-sa54 001011xxxxx 128 (4x32) kwords sa215-sa218 110100xxxxx 128 (4x32) kwords sa55-sa58 001100xxxxx 128 (4x32) kwords sa219-sa222 110101xxxxx 128 (4x32) kwords sa59-sa62 001101xxxxx 128 (4x32) kwords sa223-sa226 110110xxxxx 128 (4x32) kwords sa63-sa66 001110xxxxx 128 (4x32) kwords sa227-sa230 110111xxxxx 128 (4x32) kwords sa67-sa70 001111xxxxx 128 (4x32) kwords sa231-sa234 111000xxxxx 128 (4x32) kwords sa71-sa74 010000xxxxx 128 (4x32) kwords sa235-sa238 111001xxxxx 128 (4x32) kwords sa75-sa78 010001xxxxx 128 (4x32) kwords sa239-sa242 111010xxxxx 128 (4x32) kwords sa79-sa82 010010xxxxx 128 (4x32) kwords sa243-sa246 111011xxxxx 128 (4x32) kwords sa83-sa86 010011xxxxx 128 (4x32) kwords sa247-sa250 111100xxxxx 128 (4x32) kwords sa87-sa90 010100xxxxx 128 (4x32) kwords sa251-sa254 111101xxxxx 128 (4x32) kwords sa91-sa94 010101xxxxx 128 (4x32) kwords sa255-sa258 111110xxxxx 128 (4x32) kwords sa95-sa98 010110xxxxx 128 (4x32) kwords sa259 11111100xxx 32 kwords sa99-sa102 010111xxxxx 128 (4x32) kwords sa260 11111101xxx 32 kwords sa103-sa106 011000xxxxx 128 (4x32) kwords sa261 11111110xxx 32 kwords sa107-sa110 011001xxxxx 128 (4x32) kwords sa262 11111111000 4 kwords sa111-sa114 011010xxxxx 128 (4x32) kwords sa263 11111111001 4 kwords sa115-sa118 011011xxxxx 128 (4x32) kwords sa264 11111111010 4 kwords sa119-sa122 011100xxxxx 128 (4x32) kwords sa265 11111111011 4 kwords sa123-sa126 011101xxxxx 128 (4x32) kwords sa127-sa130 011110xxxxx 128 (4x32) kwords
42 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) table 10.13 pl129j boot sector/sector block addresses for protection/unprotection ce1# control ce2# control sector group a21-12 sector/sector block size sector group a21-12 sector/sector block size sa1-0 0000000000 4 kwords sa2-0?sa2-3 00000xxxxx 128 (4x32) kwords sa1-1 0000000001 4 kwords sa2-4?sa2-7 00001xxxxx 128 (4x32) kwords sa1-2 0000000010 4 kwords sa2-8?sa2-11 00010xxxxx 128 (4x32) kwords sa1-3 0000000011 4 kwords sa2-12?sa2-15 00011xxxxx 128 (4x32) kwords sa1-4 0000000100 4 kwords sa2-16?sa2-19 00100xxxxx 128 (4x32) kwords sa1-5 0000000101 4 kwords sa2-20?sa2-23 00101xxxxx 128 (4x32) kwords sa1-6 0000000110 4 kwords sa2-24?sa2-27 00110xxxxx 128 (4x32) kwords sa1-7 0000000111 4 kwords sa2-28?sa2-31 00111xxxxx 128 (4x32) kwords sa1-8 0000001xxx 32 kwords sa2-32?sa2-35 01000xxxxx 128 (4x32) kwords sa1-9 0000010xxx 32 kwords sa2-36?sa2-39 01001xxxxx 128 (4x32) kwords sa1-10 0000011xxx 32 kwords sa2-40?sa2-43 01010xxxxx 128 (4x32) kwords sa1-11 - sa1-14 00001xxxxx 128 (4x32) kwords sa2-44?sa2-47 01011xxxxx 128 (4x32) kwords sa1-15 - sa1-18 00010xxxxx 128 (4x32) kwords sa2-48?sa2-51 01100xxxxx 128 (4x32) kwords sa1-19 - sa1-22 00011xxxxx 128 (4x32) kwords sa2-52?sa2-55 01101xxxxx 128 (4x32) kwords sa1-23 - sa1-26 00100xxxxx 128 (4x32) kwords sa2-56?sa2-59 01110xxxxx 128 (4x32) kwords sa1-27 - sa1-30 00101xxxxx 128 (4x32) kwords sa2-60?sa2-63 01111xxxxx 128 (4x32) kwords sa1-31 - sa1-34 00110xxxxx 128 (4x32) kwords sa2-64?sa2-67 10000xxxxx 128 (4x32) kwords sa1-35 - sa1-38 00111xxxxx 128 (4x32) kwords sa2-68?sa2-71 10001xxxxx 128 (4x32) kwords sa1-39 - sa1-42 01000xxxxx 128 (4x32) kwords sa2-72?sa2-75 10010xxxxx 128 (4x32) kwords sa1-43 - sa1-46 01001xxxxx 128 (4x32) kwords sa2-76?sa2-79 10011xxxxx 128 (4x32) kwords sa1-47 - sa1-50 01010xxxxx 128 (4x32) kwords sa2-80?sa2-83 10100xxxxx 128 (4x32) kwords sa1-51 - sa1-54 01011xxxxx 128 (4x32) kwords sa2-84?sa2-87 10101xxxxx 128 (4x32) kwords sa1-55 - sa1-58 01100xxxxx 128 (4x32) kwords sa2-88?sa2-91 10110xxxxx 128 (4x32) kwords sa1-59 - sa1-62 01101xxxxx 128 (4x32) kwords sa2-92?sa2-95 10111xxxxx 128 (4x32) kwords sa1-63 - sa1-66 01110xxxxx 128 (4x32) kwords sa2-96?sa2-99 11000xxxxx 128 (4x32) kwords sa1-67 - sa1-70 01111xxxxx 128 (4x32) kwords sa2-100?sa2-103 11001xxxxx 128 (4x32) kwords sa1-71 - sa1-74 10000xxxxx 128 (4x32) kwords sa2-104?sa2-107 11010xxxxx 128 (4x32) kwords sa1-75 - sa1-78 10001xxxxx 128 (4x32) kwords sa2-108?sa2-111 11011xxxxx 128 (4x32) kwords sa1-79 - sa1-82 10010xxxxx 128 (4x32) kwords sa2-112?sa2-115 11100xxxxx 128 (4x32) kwords sa1-83 - sa1-86 10011xxxxx 128 (4x32) kwords sa2-116?sa2-119 11101xxxxx 128 (4x32) kwords sa1-87 - sa1-90 10100xxxxx 128 (4x32) kwords sa2-120?sa2-123 11110xxxxx 128 (4x32) kwords sa1-91 - sa1-94 10101xxxxx 128 (4x32) kwords sa2-124 1111100xxx 32 kwords sa1-95 - sa1-98 10110xxxxx 128 (4x32) kwords sa2-125 1111101xxx 32 kwords sa1-99 - sa1-102 10111xxxxx 128 (4x32) kwords sa2-126 1111110xxx 32 kwords sa1-103 - sa1-106 11000xxxxx 128 (4x32) kwords sa2-127 1111111000 4 kwords sa1-107 - sa1-110 11001xxxxx 128 (4x32) kwords sa2-128 1111111001 4 kwords sa1-111 - sa1-114 11010xxxxx 128 (4x32) kwords sa2-129 1111111010 4 kwords sa1-115 - sa1-118 11011xxxxx 128 (4x32) kwords sa2-130 1111111011 4 kwords sa1-119 - sa1-122 11100xxxxx 128 (4x32) kwords sa2-131 1111111100 4 kwords sa1-123 - sa1-126 11101xxxxx 128 (4x32) kwords sa2-132 1111111101 4 kwords sa1-127 - sa1-130 11110xxxxx 128 (4x32) kwords sa2-133 1111111110 4 kwords sa1-131 - sa1-134 11111xxxxx 128 (4x32) kwords sa2-134 1111111111 4 kwords
september 22, 2006 S29PL-J_00_a9 S29PL-J 43 data sheet (advance information) 10.9 selecting a sector protection mode table 10.14 pl064j boot sector/sector block addresses for protection/unprotection sector a21-a12 sector/sector block size sa0 0000000000 4 kwords sa1 0000000001 4 kwords sa2 0000000010 4 kwords sa3 0000000011 4 kwords sa4 0000000100 4 kwords sa5 0000000101 4 kwords sa6 0000000110 4 kwords sa7 0000000111 4 kwords sa8 0000001xxx 32 kwords sa9 0000010xxx 32 kwords sa10 0000011xxx 32 kwords sa11-sa14 00001xxxxx 128 (4x32) kwords sa15-sa18 00010xxxxx 128 (4x32) kwords sa19-sa22 00011xxxxx 128 (4x32) kwords sa23-sa26 00100xxxxx 128 (4x32) kwords sa27-sa30 00101xxxxx 128 (4x32) kwords sa31-sa34 00110xxxxx 128 (4x32) kwords sa35-sa38 00111xxxxx 128 (4x32) kwords sa39-sa42 01000xxxxx 128 (4x32) kwords sa43-sa46 01001xxxxx 128 (4x32) kwords sa47-sa50 01010xxxxx 128 (4x32) kwords sa51-sa54 01011xxxxx 128 (4x32) kwords sa55-sa58 01100xxxxx 128 (4x32) kwords sa59-sa62 01101xxxxx 128 (4x32) kwords sa63-sa66 01110xxxxx 128 (4x32) kwords sa67-sa70 01111xxxxx 128 (4x32) kwords sa71-sa74 10000xxxxx 128 (4x32) kwords sa75-sa78 10001xxxxx 128 (4x32) kwords sa79-sa82 10010xxxxx 128 (4x32) kwords sa83-sa86 10011xxxxx 128 (4x32) kwords sa87-sa90 10100xxxxx 128 (4x32) kwords sa91-sa94 10101xxxxx 128 (4x32) kwords sa95-sa98 10110xxxxx 128 (4x32) kwords sa99-sa102 10111xxxxx 128 (4x32) kwords sa103-sa106 11000xxxxx 128 (4x32) kwords sa107-sa110 11001xxxxx 128 (4x32) kwords sa111-sa114 11010xxxxx 128 (4x32) kwords sa115-sa118 11011xxxxx 128 (4x32) kwords sa119-sa122 11100xxxxx 128 (4x32) kwords sa123-sa126 11101xxxxx 128 (4x32) kwords sa127-sa130 11110xxxxx 128 (4x32) kwords sa131 1111100xxx 32 kwords sa132 1111101xxx 32 kwords sa133 1111110xxx 32 kwords sa134 1111111000 4 kwords sa135 1111111001 4 kwords sa136 1111111010 4 kwords sa137 1111111011 4 kwords sa138 1111111100 4 kwords sa139 1111111101 4 kwords sa140 1111111110 4 kwords sa141 1111111111 4 kwords
44 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) the device is shipped with all sectors unprotect ed. optional spansion programming services enable programming and protecting sectors at the factory prior to shipping the device. contact your local sales office for details. it is possible to determine whether a sect or is protected or unprotected. see the table 10.9, secured silicon sector addresses on page 39 for details. 11. sector protection the pl127j, pl129j, pl064j, and pl032j features seve ral levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: 11.1 persistent sector protection a command sector protection method that replac es the old 12 v controlled protection method. 11.2 password sector protection a highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted 11.3 wp# hardware protection a write protect pin that can prevent program or er ase operations in sectors sa1-133, sa1-134, sa2-0 and sa2-1. the wp# hardware protection feature is always avail able, independent of the software managed protection method chosen. 11.4 selecting a sector protection mode all parts default to operate in the pe rsistent sector protection mode. t he customer must then choose if the persistent or password protection method is most desirable. there are two one-time programmable non- volatile bits that define which sector protection met hod will be used. if the pers istent sector protection method is desired, programming the pe rsistent sector protection mode locking bit permanently sets the device to the persistent sector pr otection mode. if the password sect or protection method is desired, programming the password mode locking bit permanently sets the device to the password sector protection mode. it is not possible to switch between the two pr otection modes once a locking bit has been set. one of the two modes must be selected when the device is firs t programmed. this prevents a program or virus from later setting the password mode locking bit, whic h would cause an unexpected shift from the default persistent sector protection mode in to the password protection mode. the device is shipped with all sectors unprotect ed. optional spansion programming services enable programming and protecting sectors at the factory prior to shipping the device. contact your local sales office for details. it is possible to determine whether a sector is protected or unprotected. see autoselect mode on page 39 for details. table 10.15 sector protection schemes dyb ppb ppb lock sector state 0 0 0 unprotected?ppb and dyb are changeable 0 0 1 unprotected?ppb not changeable, dyb is changeable 010 protected?ppb and dyb are changeable 100 110 011 protected?ppb not changeable, dyb is changeable 101 111
september 22, 2006 S29PL-J_00_a9 S29PL-J 45 data sheet (advance information) 12. persistent sector protection the persistent sector protection me thod replaces the 12 v controlled protection method in previous flash devices. this new method provides three different sector protection states: ? persistently locked?the sector is protected and cannot be changed. ? dynamically locked?the sector is protecte d and can be changed by a simple command. ? unlocked?the sector is unprotected and can be changed by a simple command. to achieve these states, thre e types of ?bits? are used: ? persistent protection bit ? persistent protection bit lock ? persistent sector protection mode locking bit 12.1 persistent protection bit (ppb) a single persistent (non-volatile) protection bit is assigned to a maximum four sectors (see the sector address tables for specific sector pr otection groupings). all 4 kword boot-b lock sectors have individual sector persistent protection bits (ppbs) for greater flexib ility. each ppb is individually modifiable through the ppb write command. the device erases all ppbs in parallel. if any ppb requi res erasure, the device must be instructed to preprogram all of the sector ppbs prior to ppb erasur e. otherwise, a previously erased sector ppbs can potentially be over-erased. the flash device does not ha ve a built-in means of preventing sector ppbs over- erasure. 12.2 persistent protection bit lock (ppb lock) the persistent protection bit lock (ppb lock) is a gl obal volatile bit. when set to ?1?, the ppbs cannot be changed. when cleared (?0?), the ppbs are changeable. there is only one ppb lock bit per device. the ppb lock is cleared after power-up or hardware reset. there is no command sequence to unlock the ppb lock. 12.3 dynamic protection bit (dyb) a volatile protection bit is assigned for each sector. a fter power-up or hardware reset, the contents of all dybs is ?0?. each dyb is individually modifiable through the dyb write command. when the parts are first sh ipped, the ppbs are cleared, the dybs are cleared , and ppb lock is defaulted to power up in the cleared state ? meaning the ppbs are changeable. when the device is first powered on the dybs power up cleared (sectors not protec ted). the protection state for each sector is de termined by the logical or of the ppb and the dyb related to that sector. for the sectors that have the ppbs cleared, the dybs control whether or not the sector is prot ected or unprotected. by issuing the dyb write command sequences, the dybs will be set or cleared, thus placing each sector in the protected or unprotected st ate. these are the so-called dynamic lo cked or unlocked states. they are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. this allows software to easily protect se ctors against inadvertent changes yet does not prevent the easy removal of protection when changes are need ed. the dybs maybe set or cleared as often as needed. the ppbs allow for a more static, and difficult to change, level of prot ection. the ppbs retain their state across power cycles because they are non-volatile. indi vidual ppbs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. the ppbs are also limited to 100 erase cycles. the ppb lock bit adds an additional level of protec tion. once all ppbs are programmed to the desired settings, the ppb lock may be set to ?1?. settin g the ppb lock disables all pr ogram and erase commands to the non-volatile ppbs. in effect, the ppb lock bit locks the ppbs into thei r current state. the only way to clear the ppb lock is to go through a power cycle. syst em boot code can determine if any changes to the ppb are needed; for example, to allow new system code to be downloaded. if no changes are needed then the boot code can set the ppb lock to disable any further changes to the ppbs during system operation.
46 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) the wp#/acc write prot ect pin adds a final level of hardware protection to sectors sa1-133, sa1-134, sa2- 0 and sa2-1. when this pin is low it is not possible to change the contents of thes e sectors. these sectors generally hold system boot code. t he wp#/acc pin can preven t any changes to the boot code th at could override the choices made while setting up se ctor protection during system initialization. for customers who are concerned about malicious viruses t here is another level of se curity - the persistently locked state. to persistently protect a given sector or sector group, the ppbs associated with that se ctor need to be set to ?1?. once all ppbs ar e programmed to the desired settings, the ppb lock should be set to ?1?. setting the ppb lock automatically disables all program and erase commands to the non-volatile ppbs. in effect, the ppb lock ?freezes? the ppbs in to their current state. the only way to clear the ppb lock is to go through a power cycle. it is possible to have sectors that hav e been persistently locked, and sectors th at are left in the dynamic state. the sectors in the dynamic state are al l unprotected. if there is a need to protect some of them, a simple dyb write command sequence is all that is necessary. th e dyb write command for the dynamic sectors switch the dybs to signify protected and unprotected, respecti vely. if there is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lo ck bit must be disabled by either putting the device th rough a power-cycle, or hard ware reset. the ppbs can th en be changed to reflect the desired settings. setting the ppb lock bit once again will lock the ppbs, and the device operates normally again. the best protection is achieved by executing the ppb lock bit set command early in the boot code, and protect the boot code by holding wp#/acc = vil. table 17 contains all possible combi nations of the dyb, ppb, and ppb lock relating to the status of the sector. in summary, if the ppb is se t, and the ppb lock is set, the sector is protected and the pr otection c an not be removed until the next power cycle clears the ppb lock. if the ppb is cl eared, the sector can be dynamically locked or unlocked. the dyb then controls whether or not the sector is protected or unprotected. if the user attempts to program or erase a protected sector , the device ignores the command and returns to read mode. a program command to a protected sector enables status polling for approximately 1 s before the device returns to read mode without having modified the contents of the protected sector. an erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mode without having erased the protected sector. the programming of the dyb, ppb, and ppb lock for a given sector c an be verified by writing a dyb/ppb/ ppb lock verify command to th e device. there is an alte rnative means of reading th e protection status. take reset# to vil and hold we# at v ih . (the high voltage a9 autoselect mode also works for reading the status of the ppbs). scanning the addresses (a18?a11) while (a6, a1, a0) = (0, 1, 0) will produce a logical ?1? code at device output dq0 for a protected sector or a ?0 ? for an unprotected sector. in this mode, the other addresses are don?t cares. address location with a1 = vil are reserved for autoselect manufacturer and device codes. 12.4 persistent sector protection mode locking bit like the password mode locking bit, a persistent sector protection mode locking bit exists to guarantee that the device remain in software sector protection. once set, the persistent sector protection locking bit prevents programming of the password protection mode locking bit. this guarantees that a hacker could not place the device in password protection mode.
september 22, 2006 S29PL-J_00_a9 S29PL-J 47 data sheet (advance information) 13. password protection mode the password sector protection mode method allows an even higher level of securi ty than the persistent sector protection mode. there are two main differen ces between the persistent sector protection and the password sector protection mode: when the device is first power ed on, or comes out of a reset cycle, t he ppb lock bit set to the locked state, rather than cleared to the unlocked state. the only means to clear the ppb lo ck bit is by writing a unique 64-bit password to the device. the password sector protection meth od is otherwise identical to the persistent sector protection method. a 64-bit password is the only additi onal tool utilized in this method. once the password mode locking bit is set, the pa ssword is permanently set with no means to read, program, or erase it. the passwor d is used to clear the ppb lock bi t. the password unlock command must be written to the flash, along with a password. the fl ash device internally compares the given password with the pre-programmed password. if they match, the ppb lo ck bit is cleared, and the ppbs can be altered. if they do not match, the flash device does nothing. there is a built-in 2 s delay for each ?password check.? this delay is intended to thwart an y efforts to run a program that tries all possible combinations in order to crack the password. 13.1 password and password mode locking bit in order to select the password sector protection sche me, the customer must first program the password. the password may be correlated to the unique electronic serial number (esn) of the particular flash device. each esn is different for every flash device; theref ore each password should be different for every flash device. while programming in the password region, th e customer may perform password verify operations. once the desired password is programmed in, the cust omer must then set the password mode locking bit. this operation achieves two objectives: permanently sets the device to operate using the passwor d protection mode. it is not possible to reverse this function. disables all further commands to the password regi on. all program, and read operations are ignored. both of these objectives are important, and if not care fully considered, may lead to unrecoverable errors. the user must be sure that the passwo rd protection method is desired when setting the password mode locking bit. more importantly, the user must be sure that the password is correct when the password mode locking bit is set. due to the fact that read operations are dis abled, there is no means to verify what the password is afterwards. if the password is lost after setting the pa ssword mode locking bit, there will be no way to clear the ppb lock bit. the password mode locking bit, once set, prevents reading the 64-bit password on the dq bus and further password programming. the password mode locking bit is not erasable. once password mode locking bit is programmed, the persistent sector protection locking bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 13.2 64-bit password the 64-bit password is located in its own memory spac e and is accessible through the use of the password program and verify commands (see ?password veri fy command?). the password function works in conjunction with the password mode locking bit, whic h when set, prevents the password verify command from reading the contents of the password on the pins of the device.
48 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 13.3 write protect (wp#) the write protect feature provides a hardware method of protecting the upper two and lower two sectors without using v id . this function is provided by the wp# pin and overrides the previously discussed high voltage sector protection on page 48 method. if the system asserts v il on the wp#/acc pin, the device disables program and erase functions in the two outermost 4 kword sectors on both ends of the flash a rray independent of whether it was previously protected or unprotected. if the system asserts v ih on the wp#/acc pin, the device reverts the upper two and lower two sectors to whether they were last set to be protected or unprotecte d. that is, sector protection or unpro tection for these sectors depends on whether they were last protec ted or unprotected using the method described in the high voltage sector protection on page 48 . note that the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. 13.3.1 persistent protection bit lock the persistent protection bit (ppb) lo ck is a volatile bit that reflects the state of the password mode locking bit after power-up rese t. if the password mode lock bit is also set after a hardware re set (reset# asserted) or a power-up reset, the only means for clearing the ppb lock bit in password protection mode is to issue the password unlock command. succe ssful execution of the password unlock command clears the ppb lock bit, allowing for sector ppbs modifications. asserting reset#, taking the devi ce through a power-on reset, or issuing the ppb lock bit set command se ts the ppb lock bit to a ?1? when the password mode lock bit is not set. if the password mode locking bit is not set, including pe rsistent protection mode, the ppb lock bit is cleared after power-up or hardware reset. the ppb lock bit is set by issui ng the ppb lock bit set command. once set the only means for clearing the ppb lock bit is by issuing a hardware or power-up reset. the password unlock command is ignored in persistent protection mode. 13.4 high voltage sector protection sector protection and unprotection may also be impl emented using programming equipment. the procedure requires high voltage (v id ) to be placed on the r eset# pin. refer to figure 13.1 on page 49 for details on this procedure. note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle.
september 22, 2006 S29PL-J_00_a9 S29PL-J 49 data sheet (advance information) figure 13.1 in-system sector protection/se ctor unprotection algorithms sector protect: write 60h to sector address with a7-a0 = 00000010 set up sector address wait 150 s verify sector protect: write 40h to sector address with a7-a0 = 00000010 read from sector address with a7-a0 = 00000010 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a7-a0 = 01000010 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a7-a0 = 00000010 read from sector address with a7-a0 = 00000010 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1 device failed remove v id from reset# write reset command sector protect complete device failed remove v id from reset# write reset command sector protect complete
50 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 13.5 temporary sector unprotect this feature allows temporary unprotection of previo usly protected sectors to change data in-system. the sector unprotect mode is activate d by setting the reset# pin to v id . during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the reset# pin, all the prev iously protected sector s are protected again. figure 13.2 on page 50 shows the algorithm, and figure 21.1 on page 81 shows the timing diagrams, for this feature. while ppb lock is set, the device cannot enter the tempor ary sector unprotection mode. figure 13.2 temporary sector unprotect operation notes: 1. all protected sectors unprotected (if wp#/acc = v il , upper two and lower two sectors will remain protected). 2. all previously protected sectors are protected once again 13.6 secured silicon sector flash memory region the secured silicon sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn) the 128-word secured silicon sector is divided into 64 factory-lockable words that can be programmed and locked by the customer. the secured silicon sector is located at addresses 000000h-00007fh in both pe rsistent protection mode and password protection mode. indicator bits dq6 and dq7 are used to indicate the factory-locked and customer locked status of the part. the system accesses the secured silicon sector through a command sequence (see the enter/exit secured silicon sector command sequence on page 56 ). after the system has writt en the enter secured silicon sector command sequence, it may read the secured silicon sector by using the addresses normally occupied by the boot se ctors. this mode of operation continues un til the system issues the exit secured silicon sector command sequence, or until power is re moved from the device. once the enter secsi sector command sequence has been entered, the standard array cannot be accessed until the exit secsi sector command has been entered or the device has been reset. on power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. note that the acc function and unlock bypass modes are not available when the secured silicon sector is enabled. start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1)
september 22, 2006 S29PL-J_00_a9 S29PL-J 51 data sheet (advance information) 13.6.1 factory-locked area (64 words) the factory-locked area of the secured silicon sector (000000h-00003fh) is locked w hen the part is shipped, whether or not the area was programmed at the factory. the secured silicon sector factory-locked indicator bit (dq7) is permanently set to a ?1?. optional sp ansion programming services can program the factory- locked area with a random esn, a customer-defined code , or any combination of the two. because only spansion can program and protect the factory-locked area , this method ensures the security of the esn once the product is shipped to the field. contact your local sales office for details on using spansion?s programming services. note that the acc function and unlock bypa ss modes are not available when the secured silicon sector is enabled. 13.6.2 customer-lockable area (64 words) the customer-lockable area of the secured silicon se ctor (000040h-00007fh) is sh ipped unprotected, which allows the customer to program and optionally lock t he area as appropriate for the application. the secured silicon sector customer-locked indica tor bit (dq6) is shipped as ?0? and can be permanently locked to ?1? by issuing the secured silicon protection bit program comm and. the secured silicon sector can be read any number of times, but can be programmed and locked only once. note that the accelerated programming (acc) and unlock bypass functions are not availabl e when programming the secured silicon sector. the customer-lockable secured silicon sector area can be protected using one of the following procedures: ? write the three-cycle enter secured silicon sector region command sequence, and then follow the in- system sector protect al gorithm as shown in figure 13.1 on page 49 , except that reset# may be at either v ih or v id . this allows in-system protecti on of the secured silicon sect or region without raising any device pin to a high voltage. note that this met hod is only applicable to the secured silicon sector. ? to verify the protect/unprotect status of the secured silicon sector, follow the algorithm shown in figure on page 51 . ? once the secured silicon sector is locked and verifi ed, the system must write the exit secured silicon sector region command sequence to return to reading and writing the remainder of the array. the secured silicon sector lock must be used with caution since, once locked, there is no procedure available for unlocking the secured silicon sector area and none of the bits in the secured silicon sector memory space can be modified in any way. 13.6.3 secured silicon s ector protection bits the secured silicon sector protection bits prevent programming of the se cured silicon sector memory area. once set, the secured silicon sector memory area contents are non-modifiable. figure 13.3 secured silicon sector protect verify write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 s read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete
52 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 13.7 hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be c aused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. 13.7.1 low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the cont rol pins to prevent uni ntentional writes when v cc is greater than v lko . 13.7.2 write pulse ?g litch? protection noise pulses of less than 3 ns (typical) on oe#, ce#, (c e1#, ce2# in pl129j) or we# do not initiate a write cycle. 13.7.3 logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# (ce1# = ce2# in pl129j)= v ih or we# = v ih . to initiate a write cycle, ce# (ce1# / ce2# in pl 129j) and we# must be a logical zero while oe# is a logical one. 13.7.4 power-up write inhibit if we# = ce# (ce1#, ce2# in pl129j) = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. 14. common flash memory interface (cfi) the common flash in terface (cfi) specification outlines device and host system software in terrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device -independent, jedec id-independent, and forward- and backward-compatible for the specifie d flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi info rmation at the addresses given in table 14.1 on page 53 to table 14.4 on page 54 . to terminate reading cf i data, the system must write the reset command. the cfi query mode is not accessible when the device is executing an embedded program or embedded erase algorithm. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in table 14.1 to table 14.4 . the system must write the reset command to return the device to reading array data. for further information, please refer to the cfi specificat ion and cfi publication 100. contact your local sales office for copies of these documents.
september 22, 2006 S29PL-J_00_a9 S29PL-J 53 data sheet (advance information) table 14.1 cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) table 14.2 system interface string addresses data description 1bh 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0003h typical timeout per single byte/word write 2 n s 20h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 0009h typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0004h max. timeout for byte/word write 2 n times typical 24h 0000h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
54 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) table 14.3 device geometry definition addresses data description 27h 0018h (pl127j) 0018h (pl129j) 0017h (pl064j) 0016h (pl032j) device size = 2 n byte 28h 29h 0001h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0000h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specificat ion or cfi publication 100) 31h 00fdh (pl127j) 00fdh (pl129j) 007dh (pl064j) 003dh (pl032j) erase block region 2 information (refer to the cfi specificat ion or cfi publication 100) 32h 33h 34h 0000h 0000h 0001h 35h 36h 37h 38h 0007h 0000h 0020h 0000h erase block region 3 information (refer to the cfi specificat ion or cfi publication 100) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to the cfi specificat ion or cfi publication 100) table 14.4 primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii (re flects modifications to the silicon) 44h 0033h minor version number, ascii (reflects modifications to the cfi table) 45h tbd address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon revision number (bits 7-2) 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 0007h (plxxxj) sector protect/unprotect scheme 07 = advanced sector protection 4ah 00e7h (pl127j) 00e7h (pl129j) 0077h (pl064j) 003fh (pl032j) simultaneous operation 00 = not supported, x = number of sectors excluding bank 1 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0002h (plxxxj) page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv
september 22, 2006 S29PL-J_00_a9 S29PL-J 55 data sheet (advance information) 15. command definitions writing specific address and data co mmands or sequences into the co mmand register initiates device operations. table 15.1 on page 62 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. a reset command is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce# (ce1# / ce2# in pl129j), whichever happens later. all data is latched on the rising edge of we# or ce# (ce1# / ce2# in pl129j), whichever happens first. refer to ac characteristic on page 72 for timing diagrams. 15.1 reading array data the device is automatically set to reading array data af ter device power-up. no commands are required to retrieve data. each bank is ready to read array da ta after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the corresponding bank enters the erase-suspend- read mode, after which the system can read data fr om any non-erase-suspended sector within the same bank. the system can read array data using the standard read timing, exce pt that if it reads at an address within erase-suspended sectors, the devi ce outputs status data. after comp leting a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see erase suspend/erase resume commands on page 60 for more information. after the device accepts a program suspend comm and, the corresponding bank enters the program- suspend-read mode, after which t he system can read data from any no n-program-suspended sector within the same bank. see program suspend/program resume commands on page 61 for more information. the system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if dq5 goes high during an active program or er ase operation, or if the bank is in the autoselect mode. see the next section, reset command on page 56 , for more information. see also requirements for reading array data on page 20 for more informa tion. the table ac characteristic on page 72 provides the read parameters, and figure 16.2 on page 66 shows the timing diagram. 4fh 0001h top/bottom boot sector flag 00h = uniform device, 01h = both top and bottom boot with write protect, 02h = bottom boot device, 03h = top boot device, 04h = both top and bottom 50h 0001h program suspend 0 = not supported, 1 = supported 57h 0004h bank organization 00 = data at 4ah is zero, x = number of banks 58h 0027h (pl127j) 0027h (pl129j) 0017h (pl064j) 000fh (pl032j) bank 1 region information x = number of sectors in bank 1 59h 0060h (pl127j) 0060h (pl129j) 0030h (pl064j) 0018h (pl032j) bank 2 region information x = number of sectors in bank 2 5ah 0060h (pl127j) 0060h (pl129j) 0030h (pl064j) 0018h (pl032j) bank 3 region information x = number of sectors in bank 3 5bh 0027h (pl127j) 0027h (pl129j) 0017h (pl064j) 000fh (pl032j) bank 4 region information x = number of sectors in bank 4 table 14.4 primary vendor-specific extended query (continued) addresses data description
56 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 15.2 reset command writing the reset command resets the banks to the read or erase-suspend-read mode . address bits are don?t cares for this command. the reset command may be written between the s equence cycles in an erase command sequence before erasing begins. this resets the bank to which the syst em was writing to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be writt en between the s equence cycles in a progra m command sequence before programming begins. this resets the bank to which t he system was writing to the read mode. if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase-su spend-read mode. once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequ ence cycles in an autose lect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase susp end mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in erase suspend and program-suspend-read mode if that bank was in program suspend). 15.3 autoselect command sequence the autoselect command sequence allows the host sys tem to access the manufacturer and device codes, and determine whether or not a sector is protected. the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the device is actively programming or erasing in the other bank. the autoselect command sequence is in itiated by first writing two unlock c ycles. this is followed by a third write cycle that contains the bank address and the autos elect command. the bank then enters the autoselect mode. the system may read any num ber of autoselect codes without reinitiating the command sequence. table 15.1 on page 62 shows the address and data requirem ents. to determine sector protection information, the system must write to the appropri ate bank address (ba) and sector address (sa). table 10.4 on page 21 shows the address range and bank number associated with each sector. the system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in erase suspend). 15.4 enter/exit secured silic on sector command sequence the secured silicon sector region provides a secured data area containing a random, eight word electronic serial number (esn). the system can access the secured silicon sector region by issu ing the three-cycle enter secured silicon sector command sequence. t he device continues to a ccess the secured silicon sector region until the system issues the four-cycle exit secured silicon sector co mmand sequence. the exit secured silicon sector command sequence returns t he device to normal operation. the secured silicon sector is not accessible when the device is executing an embedded pr ogram or embedded erase algorithm. table 15.1 on page 62 shows the address and data requirement s for both command sequences. see also secured silicon sector flash memory region on page 50 for further information. note that the acc function and unlock bypass modes are not available when the secured silicon sector is enabled.
september 22, 2006 S29PL-J_00_a9 S29PL-J 57 data sheet (advance information) 15.5 word program command sequence programming is a four-bus-cycle o peration. the program co mmand sequence is initiated by writing two unlock write cycles, followed by th e program set-up command. the pr ogram address and data are written next, which in turn initia te the embed ded program algorit hm. the system is not required to provide further controls or timings. the device autom atically provides internally generated program pulses and verifies the programmed cell margin. table 15.1 on page 62 shows the address and data r equirements for the program command sequence. note that the secured silicon sector, aut oselect, and cfi functions are unavailable when a [program/erase] operation is in progress. when the embedded program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. the system can determine the status of the program operation by using dq7, dq6, or ry/by#. refer to write operation status on page 64 for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the program operat ion. the program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. note that the secured silicon sector, autoselect and cfi functions are unav ailable when the secured silicon sector is enabled. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was successful. howe ver, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? 15.5.1 unlock bypa ss command sequence the unlock bypass feature allows the system to program data to a bank faster than using the standard program command sequence. the unlock bypass command s equence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock by pass command, 20h. that bank then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initia l two unlock cycles required in the standard program command sequence, resulting in faster total programming time. table 15.1 on page 62 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (see table 15.2 on page 63 ) the device offers accelerated program operations th rough the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the de vice automatically enters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequen ce. the device uses the higher voltage on the wp#/ acc pin to accelerate the operation. note that the wp#/acc pin must not be at v hh any operation other than accelerated programming, or device damage may resu lt. in addition, the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. figure 15.1 on page 58 illustrates the algorithm for the prog ram operation. refer to the table erase/program operations on page 76 for parameters, and figure 20.6 on page 77 for timing diagrams.
58 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) figure 15.1 program operation note see table 15.1 on page 62 for program command sequence. 15.6 chip erase command sequence chip erase is a six bus cycle operatio n. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlo ck write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the emb edded erase algorithm automatically pr eprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings du ring these operations. table 15.1 on page 62 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. the system can determi ne the status of the er ase operation by using dq 7, dq6, dq2, or ry/ by#. refer to write operation status on page 64 for information on these status bits. any commands written during the ch ip erase operation are ignored. note that secured silicon sector, autoselect, and cfi functions are unavailable when a [program/erase] operation is in progress. however, note that a hardware reset immediately terminates the erase operat ion. if that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 15.2 on page 59 illustrates the algorithm for the erase operation. refer to the tables in erase/program operations on page 76 for parameters, and figure 20.8 on page 78 for timing diagrams. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
september 22, 2006 S29PL-J_00_a9 S29PL-J 59 data sheet (advance information) 15.7 sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. table 15.1 on page 62 shows the address and data requirements for t he sector erase command sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase commands ma y be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be le ss than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time-out may or may no t be accepted. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sect or erase command is written. if any command other than 30h, b0h, f0h is input during the time-out period, the normal operation will not be guaranteed. the system must rewrite the command sequence and any additional addresses and commands. note that secured silicon sector, autoselect, and cfi functions are unavailable when a [program/erase] operation is in progress. the system can monitor dq3 to determ ine if the sector erase timer has timed out (see the section on dq3: sector erase timer). the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing bank. the system can determine the status of the erase oper ation by reading dq7, dq6, dq2, or ry/by# in the erasing bank. refer to write operation status on page 64 for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset immediately terminates the erase operat ion. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 7.2 on page 15 illustrates the algorithm for the erase operation. refer to the tables in erase/program operations on page 76 for parameters, and figure 20.8 on page 78 for timing diagrams. figure 15.2 erase operation notes 1. see table 15.1 on page 62 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer. start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress
60 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 15.8 erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector eras e operation and then read data from, or program data to, any se ctor not selected for er asure. the bank address is required when writing this command. this command is valid only during the se ctor erase operation, including the 80 s time-out period during the sector er ase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a maximum of 35 s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediatel y terminates the time-out period and suspends the erase operation. addresses are ?don?t-cares ? when writing the erase suspend command. after the erase operation has been suspended, the ba nk enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any addre ss within erase-suspended se ctors produces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to write operation status on page 64 for information on these status bits. after an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq 7 or dq6 status bits, just as in the standard word program operation. refer to write operation status on page 64 for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. the device allows reading autoselect codes even at addresses within erasing sectors, since t he codes are not stored in the memory array. when the device exits the autos elect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. refer to table 10.9, secured silicon sector addresses on page 39 and autoselect command sequence on page 56 for details. to resume the sector erase operation, the system mu st write the erase resume command (address bits are don?t care). the bank address of the erase-suspended bank is required when writing this command. further writes of the resume command are ignored. another er ase suspend command can be written after the chip has resumed erasing. if the persistent sector protection mode locking bit is verified as programmed without margin, the persistent sector protection mode locking bit program comma nd should be reissued to improve program margin. if the secured silicon sector prot ection bit is verified as programmed without margin, the secured silicon sector protection bit program command should be reissued to improve program margin. ? after programming a ppb, two additional cycles are needed to determine whether the ppb has been programmed with margin. if the ppb has been programmed without margin, the prog ram command should be reissued to improve the program margin. also note that the total number of ppb program/erase cycles is limited to 100 cycles. cycling the ppbs beyond 100 cycles is not guaranteed. after erasing the ppbs, two additional cycles are nee ded to determine whether the ppb has been erased with margin. if the ppbs has been erased without margin, the erase command should be reissued to improve the program margin. the programming of either the ppb or dyb for a given sector or sector group can be verified by writing a sector protec tion status command to the device. note that there is no single command to independently verify the programming of a dyb for a given sector group.
september 22, 2006 S29PL-J_00_a9 S29PL-J 61 data sheet (advance information) 15.9 program suspend/program resume commands the program suspend command allows the system to inte rrupt an embedded programm ing operation so that data can read from any non-suspended sector. when the program suspend command is written during a programming process, the device hal ts the programming operation within t psl (program suspend latency) and updates the status bits. addresses are ?don?t-care s? when writing the program suspend command. after the programming operation has been suspended, the sy stem can read array data from any non-suspended sector. the program suspend command may also be i ssued during a programming operation while an erase is suspended. in this case, data may be read from an y addresses not in erase suspend or program suspend. if a read is needed from the secured silicon sect or area, then user must use the proper command sequences to enter and exit this region. the system may also write the autoselect command sequence when the device is in program suspend mode. the device a llows reading autoselect codes in the suspended sectors, since the codes are not stor ed in the memory array. when the device exits the autoselect mode, the device reverts to program suspend mode, and is re ady for another valid oper ation. see ?autoselect command sequence? for more information. after the pr ogram resume command is written, the device reverts to programming. the system can determine t he status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see ?write operation status? for more information. the system must write the program resume co mmand (address bits are ?don?t care?) to exit the program suspend mode and continue the programming op eration. further writes of the program resume command are ignored. another program suspend command can be written after the device has resumed programming. 15.10 command definitions tables table 15.1 on page 62 contains the memory array command definitions.
62 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) legend ba = address of bank switching to autoselect mode, bypass mode, or erase operation. determined by pl127j: amax:a20, pl064j and pl129j: amax:a19, pl032j: amax:a18. pa = program address (amax:a0). addresses latch on falling edge of we# or ce# (ce1#/ce2# for pl129j) pulse, whichever happens l ater. pd = program data (dq15:dq0) written to location pa. data latches on rising edge of we# or ce# (ce1#/ce2# for pl129j) pulse, whichever happens first. ra = read address (amax:a0). rd = read data (dq15:dq0) from location ra. sa = sector address (amax:a12) for verifying (in autoselect mode) or erasing. wd = write data. see ?configuration register? definition fo r specific write data. data latched on rising edge of we#. x = don?t care notes 1. see table 10.1 on page 20 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote read cycles. all other cycles are write operations. 4. during unlock and command cycles, when lower address bits are 555 or 2aah as shown in table, address bits higher than a11 (ex cept where ba is required) and data bits higher than dq7 are don?t cares. 5. no unlock or command cycles required when bank is reading array data. 6. the reset command is required to return to reading array (or to erase-suspend-read mode if previously in erase suspend) when bank is in autoselect mode, or if dq5 goes high (while bank is providing status information). 7. fourth cycle of autoselect command sequence is a read cycle. sy stem must provide bank address to obtain manufacturer id or de vice id information. see autoselect command sequence on page 56 for more information. 8. the data is dq6=1 for factory and customer locked and dq7=1 for factory locked. 9. the data is 00h for an unprotected sector group and 01h for a protected sector group. 10. device id must be read across cycles 4, 5, and 6. pl127j (x0eh = 2220h, x0fh = 2200h), pl129j (x0eh = 2221h, x0fh = 2200h),pl064j (x0eh = 2202h, x0fh = 2201h), pl032j (x0eh = 220ah, x0fh = 2201h). 11. system may read and program in non-erasing sectors, or enter autoselect mode, when in program/erase suspend mode. program/ erase suspend command is valid only during a sector erase operation, and requires bank address. 12. program/erase resume command is valid only during erase suspend mode, and requires bank address. 13. command is valid when device is ready to re ad array data or when device is in autoselect mode. 14. wp#/acc must be at v id during the entire operation of command. 15. unlock bypass entry command is required prior to any unlock by pass operation. unlock bypass reset command is required to ret urn to the reading array. table 15.1 memory array command definitions command (notes) cycles bus cycles (notes 1 ? 4 ) addr data addr data addr data addr data addr data addr data read (5) 1ra rd reset (6) 1xxx f0 autoselect (note 7) manufacturer id 4 555 aa 2aa 55 (ba) 555 90 (ba) x00 01 device id (10) 6 555 aa 2aa 55 (ba) 555 90 (ba) x01 227e (ba) x0e (10) (ba) x0f (10) secured silicon sector factory protect (8) 4 555 aa 2aa 55 (ba) 555 90 x03 (8) sector group protect verify (9) 4 555 aaa 2aa 55 (ba) 555 90 (sa) x02 xx00/ xx01 program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (11) 1ba b0 program/erase resume (12) 1ba 30 cfi query (13) 155 98 accelerated program (15) 2xx a0 pa pd unlock bypass entry (15) 3 555 aa 2aa 55 555 20 unlock bypass program (15) 2xx a0 pa pd unlock bypass erase (15) 2xx80xx10 unlock bypass cfi (13)(15) 1xx 98 unlock bypass reset (15) 2xxx 90 xxx 00
september 22, 2006 S29PL-J_00_a9 S29PL-J 63 data sheet (advance information) legend dyb = dynamic protection bit ow = address (a7:a0) is (00011010) pd[3:0] = password data (1 of 4 portions) ppb = persistent protection bit pwa = password address. a1:a0 selects portion of password. pwd = password data being verified. pl = password protection mode lock address (a7:a0) is (00001010) rd(0) = read data dq0 for protection indicator bit. rd(1) = read data dq1 for ppb lock status. sa = sector address where security command applies. address bits amax:a12 uniquely select any sector. sl = persistent protection mode lock address (a7:a0) is (00010010) wp = ppb address (a7:a0) is (00000010) x = don?t care ppmlb = password protection mode locking bit spmlb = persistent protection mode locking bit notes 1. see table 10.1 on page 20 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote read cycles. all other cycles are write operations. table 15.2 sector protection command definitions command (notes) cycles bus cycles (notes 1 - 4 ) addr data addr data addr data addr data addr data addr data addr data reset 1 xxx f0 secured silicon sector entry (16) 3 555 aa 2aa 55 555 88 secured silicon sector exit (16) 4 555 aa 2aa 55 555 90 xx 00 secured silicon protection bit program (notes 5 , 6 ) 6 555 aa 2aa 55 555 60 ow 68 ow 48 ow rd (0) secured silicon protection bit status 5 555 aa 2aa 55 555 60 ow 48 ow rd (0) password program (notes 5 , 7 , 8 ) 4 555 aa 2aa 55 555 38 xx [0-3] pd [0-3] password verify (notes 6 , 8 , 9 ) 4 555 aa 2aa 55 555 c8 pwa [0-3] pwd [0-3] password unlock (notes 7 , 10 , 11 ) 7 555 aa 2aa 55 555 28 pwa [0] pwd [0] pwa [1] pwd [1] pwa [2] pwd [2] pwa [3] pwd [3] ppb program (notes 5 , 6 , 11 ) 6 555 aa 2aa 55 555 60 (sa) wp 68 (sa) wp 48 (sa) wp rd(0) ppb status 4 555 aa 2aa 55 555 90 (sa) wp rd (0) all ppb erase (notes 5 , 6 , 13 , 14 ) 6 555 aa 2aa 55 555 60 wp 60 (sa) 40 (sa) wp rd(0) ppb lock bit set 3 555 aa 2aa 55 555 78 ppb lock bit status (15) 4 555 aa 2aa 55 555 58 sa rd (1) dyb write (7) 4 555 aa 2aa 55 555 48 sa x1 dyb erase (7) 4 555 aa 2aa 55 555 48 sa x0 dyb status (6) 4 555 aa 2aa 55 555 58 sa rd (0) ppmlb program (notes 5 , 6 , 12 ) 6 555 aa 2aa 55 555 60 pl 68 pl 48 pl rd(0) ppmlb status (5) 5 555 aa 2aa 55 555 60 pl 48 pl rd (0) spmlb program (notes 5 , 6 , 12 ) 6 555 aa 2aa 55 555 60 sl 68 sl 48 sl rd(0) spmlb status (5) 5 555 aa 2aa 55 555 60 sl 48 sl rd (0)
64 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 4. during unlock and command cycles, when lower address bits are 555 or 2aah as shown in table, address bits higher than a11 (ex cept where ba is required) and data bits higher than dq7 are don?t cares. 5. the reset command returns device to reading array. 6. cycle 4 programs the addressed locking bit. cycles 5 and 6 va lidate bit has been fully programmed when dq0 = 1. if dq0 = 0 in cycle 6, program command must be issued and verified again. 7. data is latched on the rising edge of we#. 8. entire command sequence must be entered for each portion of password. 9. command sequence returns ffh if ppmlb is set. 10. the password is written over four consecutive cycles, at addresses 0-3. 11. a 2 s timeout is required between any two portions of password. 12. a 100 s timeout is required between cycles 4 and 5. 13. a 1.2 ms timeout is required between cycles 4 and 5. 14. cycle 4 erases all ppbs. cycles 5 and 6 validate bits have be en fully erased when dq0 = 0. if dq0 = 1 in cycle 6, erase comm and must be issued and verified again. before issuing erase command, all ppbs should be programmed to prevent ppb overerasure. 15. dq1 = 1 if ppb locked, 0 if unlocked. 16. once the secured silicon sector entry command sequence has been entered, the standar d array cannot be accessed until the exi t secsi sector command has been entered or the device has been reset. 16. write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 16.1 on page 68 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. 16.1 dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the devic e outputs on dq7 the co mplement of the datum programmed to dq7. this dq7 status also appl ies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for app roximately 1 s, then that bank returns to the read mode. during the embedded erase algorithm, data# poll ing produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the bank enters the eras e suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all se ctors selected for erasing are protected, data# polling on dq7 is active for approximately 400 s, then the bank returns to the read mode. if not all selected sectors are protected, the embedde d erase algorithm erases the unprotect ed sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a pr otected sector, the status may not be valid. when the system detects dq7 has c hanged from the complement to tr ue data, it can read valid data at dq15?dq0 on the following read cycles. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq15?dq 0 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the stat us or valid data. even if the device has completed the program or erase operation and dq7 has valid data , the data outputs on dq15?dq0 may be still invalid. valid data on dq15?dq0 will appear on successive read cycles. table 16.1 on page 68 shows the outputs for data# polling on dq7. figure 16.1 on page 65 shows the data# polling algorithm. figure 20.10 on page 79 shows the data# polling timing diagram.
september 22, 2006 S29PL-J_00_a9 S29PL-J 65 data sheet (advance information) figure 16.1 data# polling algorithm notes 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5. 16.2 ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin wh ich indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-dra in output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the devic e is actively erasing or programmi ng. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read mode. table 16.1 on page 68 shows the outputs for ry/by#. 16.3 dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the se ctor erase time-out. during an embedded program or erase algorithm operatio n, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce # to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sect ors selected for erasing are protected, dq6 toggles for approximately 400 s, then returns to reading array data. if not all se lected sectors are protected, the embedded erase algorithm erases the unprotected sect ors, and ignores the selected sectors that are protected. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start
66 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) the system can use dq6 and dq2 toget her to determine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq 6 stops toggling. howe ver, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternativ ely, the system can use dq7 (see the dq7: data# polling on page 64 ). if a program address falls within a protected sector, dq6 toggles for approximatel y 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. table 16.1 on page 68 shows the outputs for toggle bit i on dq6. figure 16.2 on page 66 shows the toggle bit algorithm. figure 20.11 on page 80 in shows the toggle bit timing diagrams. figure 20.12 on page 80 shows the differences between dq2 and dq 6 in graphical form. see also the dq2: toggle bit ii on page 67 . figure 16.2 toggle bit algorithm note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the dq6: toggle bit i on page 65 and dq2: toggle bit ii on page 67 for more information. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start
september 22, 2006 S29PL-J_00_a9 S29PL-J 67 data sheet (advance information) 16.4 dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have be en selected for erasure. (the system may use either oe# or ce# (ce1# / ce2# for pl129j) to control the read cycles.) but dq2 cannot distinguish whether the sect or is actively erasing or is er ase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 16.1 on page 68 to compare outputs for dq2 and dq6. figure 16.2 on page 66 shows the toggle bit algorithm in flowchart form, and the dq2: toggle bit ii on page 67 explains the algorithm. see also the dq6: toggle bit i on page 65 . figure 20.11 on page 80 shows the toggle bit timing diagram. figure 20.12 on page 80 shows the differences between dq2 and dq6 in graphical form. 16.5 reading toggle bits dq6/dq2 refer to figure 16.2 on page 66 for the following discussi on. whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the t oggle bit is not toggling, the device has completed the program or erase operati on. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two re ad cycles, the system determi nes that the toggle bit is still to ggling, the system also should note whet her the value of dq5 is high (see the section on dq5) . if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successf ully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 16.2 on page 66 ). 16.6 dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timi ng limit has been exceeded, dq5 produces a ?1.? under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previ ously in the erase-suspend-program mode).
68 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 16.7 dq3: sector erase timer after writing a sector erase comm and sequence, the system may read dq 3 to determ ine whether or not erasure has begun. (the sector erase ti mer does not apply to the chip eras e command.) if additional sectors are selected for erasure, the entire time-out also ap plies after each additional sector erase command. when the time-out period is complete, dq3 swit ches from a ?0? to a ?1.? see also the sector erase command sequence on page 59 . after the sector erase command is wr itten, the system should re ad the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further commands (e xcept erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? th e device will accept additional sector erase commands. to ensure the command has been accepted, the system so ftware should check the stat us of dq3 prior to and following each subsequent sector erase command. if dq 3 is high on the second status check, the last command might not have been accepted. table 16.1 shows the status of dq3 relati ve to the other status bits. notes: 1. dq5 switches to ?1? when an embedded program or embedded eras e operation has exceeded the maximum timing limits. refer to dq5: exceeded timing limits on page 67 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs array data if the system addresses a non-busy bank. table 16.1 write operation status status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode erase suspend- read erase suspended sector 1 no toggle 0 n/a toggle 1 non-erase suspended sector data data data data data 1 erase-suspend -program dq7# toggle 0 n/a n/a 0 program suspend mode (note 3) reading within program suspended sector invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) 1 reading within non-program suspended sector data data data data data 1
september 22, 2006 S29PL-J_00_a9 S29PL-J 69 data sheet (advance information) 17. absolute maximum ratings notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 17.1 on page 69 . 2. minimum dc input voltage on pins a9, oe#, reset#, and wp#/acc is ?0.5 v. during voltage transitions, a9, oe#, wp#/acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 17.1 on page 69 . maximum dc input voltage on pin a9, oe#, and reset# is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. maximum dc input voltage on wp#/acc is +9.5 v which may overshoot to +12.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 4. stresses above those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. this is a stress ratin g only; functional operation of the device at these or any other conditio ns above those indicated in the operational sections of this d ata sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability figure 17.1 maximum overshoot waveforms storage temperature plastic packages ?65c to +150c ambient temperature with power applied ?65c to +125c voltage with respect to ground v cc (note 1) ?0.5 v to +4.0 v a9 , oe# , and reset# (note 2) ?0.5 v to +13.0 v wp#/acc (note 2) ?0.5 v to +10.5 v all other pins (note 1) ?0.5 v to v cc +0.5 v output short circuit current (note 3) 200 ma 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v maximum negative overshoot waveform maximum positive overshoot waveform
70 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 18. operating ranges operating ranges define those limits between whic h the functionality of th e device is guaranteed. industrial (i) devices ambient temperature (t a ) ................?40c to +85c wireless (w) devices ambient temperature (t a ) ................?25c to +85c supply voltages v cc ...................................................2.7?3.6 v v io (see note) ........ .............. .............1.65?1.95 v (for pl127j and pl129j) or 2.7?3.6 v (for all plxxxj devices) note: for all ac and dc specifications, v io = v cc ; contact your local sales office for other v io options.
september 22, 2006 S29PL-J_00_a9 S29PL-J 71 data sheet (advance information) 19. dc characteristics notes 1. the i cc current listed is typically less than 5 ma/mhz, with oe# at v ih . 2. maximum i cc specifications are tested with v cc = v ccmax . 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 2 a. 5. not 100% tested. 6. in s29pl129j there are two ce# (ce1#, ce2#). 7. valid ce1#/ce2# conditions: (ce1# = v il, ce2# = v ih, ) or (ce1# = v ih, ce2# = v il ) or (ce1# = v ih, ce2# = v ih ) table 19.1 cmos compatible parameter parameter description (notes) test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, oe#, reset# input load current v cc = v cc max ; v id = 12.5 v 35 a i lr reset leakage current v cc = v cc max ; v id = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , oe# = v ih v cc = v cc max 1.0 a i cc1 v cc active read current ( 1 , 2 ) oe# = v ih , v cc = v cc max 5 mhz 20 30 ma 10 mhz 45 55 i cc2 v cc active write current ( 2 , 3 )oe# = v ih , we# = v il 15 25 ma i cc3 v cc standby current (2) ce#, reset#, wp#/acc = v io 0.3 v 0.2 5 a i cc4 v cc reset current (2) reset# = v ss 0.3 v 0.2 5 a i cc5 automatic sleep mode (notes 2 , 4 ) v ih = v io 0.3 v; v il = v ss 0.3 v 0.2 5 a i cc6 v cc active read-while-program current ( 1 , 2 ) oe# = v ih , 5 mhz 21 45 ma 10 mhz 46 70 i cc7 v cc active read-while-erase current ( 1 , 2 ) oe# = v ih , 5 mhz 21 45 ma 10 mhz 46 70 i cc8 v cc active program-while-erase- suspended current ( 2 , 5 ) oe# = v ih 17 25 ma i cc9 v cc active page read current (2) oe# = v ih , 8 word page read 10 15 ma v il input low voltage v io = 1.65?1.95 v (pl127j and pl129j) ?0.4 0.4 v v io = 2.7?3.6 v ?0.5 0.8 v v ih input high voltage v io = 1.65?1.95 v (pl127j and pl129j) v io ?0.4 v io +0.4 v v io = 2.7?3.6 v 2.0 v cc +0.3 v v hh voltage for acc program acceleration v cc = 3.0 v 10% 8.5 9.5 v v id voltage for autoselect and temporary sector unprotect v cc = 3.0 v 10% 11.5 12.5 v v ol output low voltage i ol = 100 a, v cc = v cc min , v io = 1.65?1.95 v (pl127j and pl129j) 0.1 v i ol = 2.0 ma, v cc = v cc min , v io = 2.7?3.6 v 0.4 v v oh output high voltage i oh = ?100 a, v cc = v cc min , v io = 1.65?1.95 v (pl127j and pl129j) v io ?0.1 v i oh = ??100 a, v io = v cc min v cc - 0.2v v v lko low v cc lock-out voltage (5) 2.3 2.5 v
72 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 20. ac characteristic 20.1 test conditions figure 20.1 test setups note diodes are in3064 or equivalent 20.2 switching waveforms table 20.1 test specifications test conditions all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times v io = 1.8 v (pl127j and pl129j) 5ns v io = 3.0 v input pulse levels v io = 1.8 v (pl127j and pl129j) 0.0 - 1.8 v v io = 3.0 v 0.0?3.0 input timing measurement reference levels v io /2 v output timing measurement reference levels v io /2 v 2.7 k c l 6.2 k 3.6 v device under te s t c l device under te s t v io = 3.0 v v io = 1.8 v (pl127j and pl129j) table 20.2 key to switching waveforms waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z)
september 22, 2006 S29PL-J_00_a9 S29PL-J 73 data sheet (advance information) figure 20.2 input waveforms and measurement levels 20.3 v cc ramp rate all dc characteristics are specified for a v cc ramp rate > 1v/100 s and v cc v ccq - 100 mv. if the v cc ramp rate is < 1v/100 s, a hardware reset required.+ 20.4 read operations notes 1. not 100% tested. 2. see figure 20.1 on page 72 and table 20.1 on page 72 for test specifications 3. measurements performed by placing a 50 ohm termination on the data pin with a bias of v cc /2. the time from oe# high to the data bus driven to v cc /2 is taken as t df . 4. s29pl129j has two ce# (ce1#, ce2#). 5. valid ce1# / ce2# conditions: (ce1# = v il ,ce2# = v ih ) or (ce1# = v ih ,ce2# = v il ) or (ce1# = v ih, ce2# = v ih ) 6. valid ce1# / ce2# transitions: (ce1# = v il ,ce2# = v ih ) or (ce1# = v ih ,ce2# = v il ) to (ce1# = ce2# = v ih ) 7. valid ce1# / ce2# transitions: (ce1# = ce2# = v ih ) to (ce1# = v il ,ce2# = v ih ) or (ce1# = v ih ,ce2# = v il ) 8. for 70 pf output load capacitance, 2 ns will be added to the above t acc ,t ce ,t pac c ,t oe values for all speed grades v io 0.0 v v io /2 v io /2 output measurement level input table 20.3 read-only operations parameter description (notes) test setup speed options unit jedec std. 55 60 65 70 t avav t rc read cycle time (1) min55606570 ns t avqv t acc address to output delay ce#, oe# = v il max55606570 ns t elqv t ce chip enable to output delay oe# = v il max55606570 ns t pac c page access time max 20 25 25 30 ns t glqv t oe output enable to output delay max 20 25 30 ns t ehqz t df chip enable to output high z (3) max 16 ns t ghqz t df output enable to output high z ( 1 , 3 ) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first (3) min 5 ns t oeh output enable hold time (1) read min 0 ns toggle and data# polling min 10 ns
74 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) figure 20.3 read operation timings notes 1. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 2. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2# figure 20.4 page read operation timings notes 1. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 2. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2# t oh t ce high z valid data high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t d addresses ce# oe# data we amax - a3 ce# oe# a2 - a0 data same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c
september 22, 2006 S29PL-J_00_a9 S29PL-J 75 data sheet (advance information) 20.5 reset note not 100% tested. figure 20.5 reset timings notes 1. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 2. s29pl129j - there are two ce# (ce1#, ce2#). in the below waveform ce# = ce1# or ce2# table 20.4 hardware reset (reset#) parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb
76 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 20.6 erase/program operations notes: 1. not 100% tested. 2. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 3. s29pl129j - there are two ce# (ce1#, ce2#). 4. see table 21.4 on page 84 for more information. table 20.5 erase and program operations parameter description speed options (ns) jedec std 55 60 65 70 unit t avav t wc write cycle time (note 1) min55606570 t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 30 35 ns t aht address hold time from ce# (ce1#, ce#2 in pl129j) or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 25 30 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 10 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# (ce1# or ce#2 in pl129j) setup time min 0 ns t wheh t ch ce# (ce1# or ce#2 in pl129j) hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 20 25 ns t sr/w latency between read and write operations min 0 ns t whwh 1 t whw h1 programming operation (note 4) ty p 6 s t whwh 1 t whw h1 accelerated programming operation (note 4) ty p 4 s t whwh 2 t whw h2 sector erase operation (note 4) typ 0.5 sec t vcs v cc setup time (note 1) min 50 s t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 ns min 35 ns t psl program suspend latency max 35 s t esl erase suspend latency max 35 s
september 22, 2006 S29PL-J_00_a9 S29PL-J 77 data sheet (advance information) 20.7 timing diagrams figure 20.6 program operation timings notes 1. pa = program address, pd = program data, d out is the true data at the program address 2. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 3. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2# figure 20.7 accelerated program timing diagram oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa wp#/acc t vhh v hh v il or v ih v il or v ih t vhh
78 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) figure 20.8 chip/sector erase operation timings notes 1. sa = sector address (for sector erase), va = valid address for reading status data (see write operation status on page 64 2. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 3. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2#. oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch status d out t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy
september 22, 2006 S29PL-J_00_a9 S29PL-J 79 data sheet (advance information) figure 20.9 back-to-back read/write cycle timings figure 20.10 data# polling timings (during embedded algorithms) note va = valid address. the illustration shows first status cycle afte r command sequence, last status read cycle, and array data re ad cycle oe# ce# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t as t rc t ce t ah valid out t oe t acc t oeh t ghwl t df valid in ce# controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w t as we# ce# oe# high z t oe high z dq7 dq6?dq0 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc
80 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) figure 20.11 toggle bit timings (during embedded algorithms) notes 1. va = valid address; not required for dq6. the illustration sh ows first two status cycle after command sequence, last status r ead cycle, and array data read cycle 2. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 3. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2# figure 20.12 dq2 vs. dq6 note dq2 toggles only when read at an address within an erase-suspended se ctor. the system may use oe# or ce# to toggle dq2 and dq6. oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by# enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
september 22, 2006 S29PL-J_00_a9 S29PL-J 81 data sheet (advance information) 21. protect/unprotect note not 100% tested. figure 21.1 temporary sector unprotect timing diagram table 21.1 temporary sector unprotect parameter description all speed options unit jedec std t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 250 ns t rsp reset# setup time for temporary sector unprotect min 4 s t rrb reset# hold time from ry/by# high for temporary sector unprotect min 4 s reset# t vidr v id v il or v ih v id v il or v ih ce# we# ry/by# t vidr t rsp program or erase command sequence t rrb
82 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) figure 21.2 sector/sector block protect and unprotect timing diagram notes 1. for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. 2. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 3. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2# sector group protect: 150 s sector group unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect/unprotect verify v id v ih
september 22, 2006 S29PL-J_00_a9 S29PL-J 83 data sheet (advance information) 21.1 controlled erase operations notes 1. not 100% tested. 2. see erase and programming performance on page 84 for more information. figure 21.3 alternate ce# controlled write (erase/program) operation timings notes 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device 4. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 5. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2# table 21.2 alternate ce# controlled er ase and program operations parameter description (notes) speed options unit jedec std 55 60 65 70 t avav t wc write cycle time (note 1) min55606570 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 30 35 ns t dveh t ds data setup time min 25 30 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# (ce1# or ce#2 in pl129j) pulse width min 35 40 ns t ehel t cph ce# (ce1# or ce#2 in pl129j) pulse width high min 20 25 ns t whwh1 t whwh1 programming operation (note 2) ty p 6 s t whwh1 t whwh1 accelerated programming operation (note 2) ty p 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy
84 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) note this parameter is defined for ce1#/ce2# recover time for read/read, program/read, and read/program operations. program/program operation are not allowed and only a single program operation is allowed at one time. figure 21.4 timing diagram for alternating between ce1# and ce2# control notes 1. typical program and erase times assume the following conditions: 25c, 3.0 v v cc , 100,000 cycles. additionally, programming typicals assume checkerboard pattern. all values are subject to change. 2. under worst case conditions of 90c, v cc = 2.7 v, 1,000,000 cycles. all va lues are subject to change. 3. the typical chip programming time is consi derably less than the maximum chip programming time listed, since most bytes progra m faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 15.1 on page 62 for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 100,000 cycles. table 21.3 ce1#/ce2# timing (s29pl129j only) parameter description all speed options unit jedec std t ccr ce1#/ce2# recover time (see note) min 0 ns table 21.4 erase and programming performance parameter typ (note 1) max (note 2) unit comments sector erase time 0.5 2 sec excludes 00h programming prior to erasure (note 4) chip erase time pl127j/129j 135 216 sec pl064j 71 113.6 sec pl032j 39 62.4 sec word program time 6 100 s excludes system level overhead (note 5) accelerated word program time 4 60 s chip program time (note 3) pl127j/129j 50.4 200 sec pl064j 25.2 50.4 sec pl032j 12.6 25.2 sec ce1# t ccr t ccr ce2#
september 22, 2006 S29PL-J_00_a9 S29PL-J 85 data sheet (advance information) 22. bga pin capacitance notes 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6.3 7 pf c out output capacitance v out = 0 7.0 8 pf c in2 control pin capacitance v in = 0 5.5 8 pf c in3 wp#/acc pin capacitance v in = 0 11 12 pf
86 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 23. physical dimensions 23.1 vbg080?80-ball fine-pitch ball gr id array 8 x 11 mm package (pl127j) 3329 \ 16-038.25b notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbg 080 jedec n/a 11.00 mm x 8.00 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.18 --- --- ball height a2 0.62 --- 0.76 body thickness d 11.00 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. ball footprint e1 5.60 bsc. ball footprint md 12 row matrix size d direction me 8 row matrix size e direction n 80 total ball count b 0.33 --- 0.43 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement (a3-a6,b3-b6,l3-l6,m3-m6) depopulated solder balls top view index mark corner 10 pin a1 c 0.05 (2x) (2x) c 0.05 e d a b a1 corner ml j k e 7 ba c ed f hg 8 7 6 5 4 3 2 1 e d1 e1 se 7 b ca c m 0.15 0.08 m 6 nx b sd bottom view side view a2 a a1 0.10 c c 0.08 c seating plane
september 22, 2006 S29PL-J_00_a9 S29PL-J 87 data sheet (advance information) 23.2 vbh064?64-ball fine-pitch ball grid array 8 x 11.6 mm package (pl127j) 3330 \ 16-038.25b notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbh 064 jedec n/a 11.60 mm x 8.00 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.18 --- --- ball height a2 0.62 --- 0.76 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. ball footprint e1 7.20 bsc. ball footprint md 12 row matrix size d direction me 10 row matrix size e direction n 64 total ball count b 0.33 --- 0.43 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement (a2-9,b1-4,b7-10,c1-k1, depopulated solder balls m2-9,c10-k10,l1-4,l7-10, g5-6,f5-6) bottom view top view side view a1 corner a2 a 10 9 10 ml j k e c 0.05 (2x) (2x) c 0.05 a1 e d 7 ba c ed f hg 8 7 6 5 4 3 2 1 e d1 e1 se 7 b ca c m 0.15 0.08 m 6 0.10 c c 0.08 nx b sd a b c seating plane a1 corner index mark
88 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 23.3 vbk048?48-ball fi ne-pitch ball grid array 8.15 x 6.15 mm package (pl032j and pl064j) 3338 \ 16-038.25b notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbk 048 jedec n/a 8.15 mm x 6.15 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.18 --- --- ball height a2 0.62 --- 0.76 body thickness d 8.15 bsc. body size e 6.15 bsc. body size d1 5.60 bsc. ball footprint e1 4.00 bsc. ball footprint md 8 row matrix size d direction me 6 row matrix size e direction n 48 total ball count b 0.33 --- 0.43 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement --- depopulated solder balls side view top view seating plane a2 a (4x) 0.10 10 d e c 0.10 a1 c b a c 0.08 bottom view a1 corner b a m 0.15 c m 7 7 6 e se sd 6 5 4 3 2 a b c d e f g 1 h b e1 d1 c 0.08 pin a1 corner index mark
september 22, 2006 S29PL-J_00_a9 S29PL-J 89 data sheet (advance information) 23.4 vbu056?56-ball fine-pitch bga 7 x 9mm package (pl064j and pl032j) 3440\ 16-038.25 \ 01.13.05 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbu 056 jedec n/a 9.00 mm x 7.00 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.17 --- --- ball height a2 0.62 --- 0.76 body thickness d 9.00 bsc. body size e 7.00 bsc. body size d1 5.60 bsc. ball footprint e1 5.60 bsc. ball footprint md 8 row matrix size d direction me 8 row matrix size e direction n 56 total ball count b 0.35 0.40 0.45 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement a1,a8,d4,d5,e4,e5,h1,h8 depopulated solder balls seating plane e1 7 se d1 e a c db e f g h 7 8 6 5 3 2 1 e 4 a1 corner 7 sd bottom view c c a d e c 0.05 (2x) c 0.05 b (2x) c 10 side view top view index mark a1 a a2 a1 corner 0.10 0.08 b a c m m c 0.08 0.15 6 nx b
90 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 23.5 ts056?20 x 14 mm, 56-pin tsop (pl127j) -x- x = a or b e/2 detail b c l 0.25mm (0.0098") bsc 0? detail a r gage line parallel to seating plane b b1 (c) 7 6 c1 with plating base metal 7 c a-b s m 0.08mm (0.0031") section b-b e 0.10 c a2 plane seating c a1 see detail b see detail b b b b b see detail a see detail a 2 standard pin out (top view) 2 n +1 n n 1 4 2 a -a- -b- 5 e 5 d1 d 6 2 3 4 5 7 8 9 ts 056 mo-142 (b) ec 56 min 0.05 0.95 0.17 0.17 0.10 0.10 18.30 19.80 0.50 0? 0.08 13.90 0.50 basic max 0.15 1.20 0.27 0.16 0.21 5? 0.20 18.50 14.10 0.70 20.20 0.23 1.05 0.20 1.00 0.22 18.40 20.00 0.60 3? 14.00 nom symbol jedec package b1 a2 a1 a d l e e d1 b c1 c 0 r n 1 notes: controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982) pin 1 identifier for standard pin out (die up). pin 1 identifier for reverse pin out (die down), ink or laser mark. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15mm (.0059") per side. dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 (0.0031") total in excess of b dimension at max. material condition. minimum space between protrusion and an adjacent lead to be 0.07 (0.0028"). these dimensions apply to the flat section of the lead between 0.10mm (.0039") and 0.25mm (0.0098") from the lead tip. lead coplanarity shall be within 0.10mm (0.004") as measured from the seating plane. dimension "e" is measured at the centerline of the leads.
september 22, 2006 S29PL-J_00_a9 S29PL-J 91 data sheet (advance information) 24. revision summary 24.1 revision a0 (january 29, 2004) initial release. 24.2 revision a1 (february 12, 2004) software features included backward compatibility with mbm29xx families. general description 48-ball bga package is not supported and was removed. ordering information model numbers for the 48-ball bg a configurations were removed. 64-ball fine pitch bga?mcp compatible an illustration was added to show the pin-out configuration. table 20 added the description of 01h for address 4fh and removed the 0004 data. table 34 provided the time units of measure fo r the erase and programming performances. 24.3 revision a2 (february 17, 2004) memory array command definitions, table corrected typo in device id. 24.4 revision a3 (february 25, 2004) architectural advantages added 3v v io for pl064j and pl032j devices. ordering information corrected the voltage rating, ball configuration, and physical dimensions for model numbers 12 and 13. connection diagrams removed the 64-ball, 8x9 mm diagram. operating ranges clarified the supply voltages that apply to th e pl127j/pl129j and all other plxxxj products. bga pin capacitance added information applicable to the c in3 symbol. package drawings removed the 9x8 mm package drawing.
92 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) 24.5 revision a4 (february 27, 2004) connection diagrams added the 56-ball 7x9 mm pinout diagram. package options updated to include the 8 x 6 mm, 48-ball fine pitch bga and 7 x 9 mm, 56-ball fine-pitch bga options. physical dimensions added the vbk048 package drawing. 24.6 revision a5 (march 15, 2004) connection diagrams changed names. 24.7 revision a6 (august 30, 2004) global removed v io , added tsop, fixed secured silicon dq bits. product selector guide updated specs in this table. ordering information updated the model number offerings. valid combinations table (128mb) corrected the package markings for the 64-ball fbga packages. added combinations for the tlc056 package on the pl064j and pl032j devices. valid combinations for bga packages (128mb) updated information in this table. package options added the 7 x 9mm 56-ball package. connection diagram 56-ball connection diagram erase/programming performance table notes 1 and 2 corrected to reflect accurate temperature ranges and cycling. 24.8 revision a7 (march 2, 2005) ordering information updated the model number offerings valid combinations table updated the package types information. figure 6, in-system sector protection/sector unprotection algorithms updated the illustration. program suspend/program resume commands new section added. made global changes to include program suspend/resume commands.
september 22, 2006 S29PL-J_00_a9 S29PL-J 93 data sheet (advance information) table 29 on page 82 added erase suspend latency. table 32, ce1#/ce2# timing (s29pl129j only) updated table and added a notes section. physical dimensions added the vbu056 package. 24.9 revision a8 (july 29, 2005) autoselect codes (high voltage method) table added note: when polling the secsi indicator bit the bank address (ba) should be set within the address range 004000h-03ffffh. autoselect codes for pl129j table added note: when polling the secsi indicator bit the a21 to a12 should be set within the address range 004000h-03ffffh. secured silicon sector flash memory region added sentence: once the enter secured silicon se ctor command sequence has been entered, the standard array cannot be accessed un til the exit secured silicon sector command has been entered or the device has been reset. sector protection command definitions table added note 16: once the secured silicon sector en try command sequence has been entered, the standard array cannot be accessed until the exit secured silic on sector command has been entered or the device has been reset. valid combinations content the same, tables consolidated to match ordering information descriptions connection diagrams section consolidated special package handling instructions and put the information before the package/pinout descriptions. added figure numbers to the connection diagram graphics. operating ranges updated operating temperatures. dc characteristics table updated v oh parameter. erase/program operations table added t esl parameter vbk048?48-ball fine-pitch ball grid array 8.15 x 6.15 mm package (pl032j and pl064j) updated the product that uses this package from pl127j to pl064j and pl032j 24.10 revision a9 (september 22, 2006) 64-ball fine-pitch bga? mcp compatible?pl127j changed ball f9 to a22
94 S29PL-J S29PL-J_00_a9 september 22, 2006 data sheet (advance information) colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansi on assumes no liability for any damages of any ki nd arising out of the use of the information in this document. copyright ? 2004-2006 spansion inc. all rights reserved. spansion, the spansion logo, mirrorbit, ornand, hd-sim, and combinatio ns thereof are trademarks of spansion inc. other names are for informational purposes only and may be trademarks of their respecti ve owners.

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